JPH046862A - Formation of lead frame - Google Patents

Abstract

PURPOSE:To easily and inexpensively mold multiple pin lead frame to be associated with an ultrahigh speed, high capacity semiconductor device by forming lead inner ends in a multi-finger array state by etching, coining it, and increasing in width a bonding surface. CONSTITUTION:Two inner ends 1a, 1a of a lead frame are reduced in width W'' of the ends 1a by etching, and a pitch P between the ends 1a and 1a is reduced to be molded that much. Then, the ends 1a are reduced in thickness T'' by coining for collapsing the ends 1a, 1b of the lead frame A by pressing while holding the pitch P as it is. The ends 1a are widened at the width W'' to W upon reduction of the thickness T, the sides are externally extended to reduce a space S'' to S between the ends 1a and 1a. The upper faces of the inner ends 1a are used as bonding surfaces.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for molding a lead frame used in a semiconductor device.

(Prior art and its problems) Conventionally, lead frames have been formed by pressing or etching, and the inner ends of the leads are formed in a multi-finger array. Etching is advantageous because it can reduce the pitch between leads.

However, when forming the inner ends of the leads using a general etching method, the space S' between the leads is at least equal to the thickness T' of the leads (S' = T'
) is the limit. Less than that (S'
<T') can be reduced to a certain extent by special methods using special equipment and techniques, but this not only increases costs but also reduces production due to variations in precision and low yields. There is a defect that is inferior to the gender. Therefore, in order to reduce the pitch P' between the leads at the inner end of the leads to accommodate the increase in the number of pins using the general etching method described above, it is necessary to reduce the upper surface width W of the leads. Since the upper surface serves as a bonding surface for bonding semiconductor chips, it is necessary to ensure a predetermined width, and there is a limit to reducing the upper surface width W.

However, in the conventional method described above, even if it is possible to form a lead frame that can accommodate an increase in pin count of 150 to 200 pins, it is difficult to form a lead frame that can accommodate an ultra-high pin count of 300 to 400 pins. Molding was impossible.

Therefore, it is an object of the present invention to provide a method for molding a lead frame that can easily and inexpensively mold a lead frame with a large number of pins that can be incorporated into an ultra-high-speed, high-capacity semiconductor device by eliminating such conventional problems. shall be.

(Means for Solving the Problems) The method for molding the lead frame of the present invention involves forming the inner ends of the leads into a multi-finger arrangement by etching, and then applying coining processing to crush the inner ends of the leads. It is characterized by widening the bonding surface.

(Function) According to the present invention, the inner end portions of the leads formed by etching can be changed to the width W' of the bonding surface by the subsequent coining process without changing the pitch P between the leads.
In other words, the etching process width W' can be made smaller than the conventional etching process width W to make one pitch P smaller than the conventional pitch P'. If the space between the leads S'
By narrowing the pitch to S, one pitch P between the leads can be made smaller than the conventional pitch P'.

(Embodiment) To explain an embodiment of the present invention with reference to the drawings, FIG. 1 shows a lead frame A that has been etched, and as shown, the inner end portion 1a of each lead 1 is formed in a multi-finger arrangement. ing.

The lead 1 and the inner end portion 1a are shown enlarged in FIGS. 2 and 3, and in FIG. 3, only the two lead inner end portions 1a and 1a are shown for convenience of explanation. The etching process is the same as the conventional one, so its explanation will be omitted, but compared to the conventional method shown in FIG. Inner end 1a, la
The pitch P between the two is made smaller than the conventional pitch P'.

Note that the space S' between the inner ends lx and la of the leads is formed to have the same lead thickness T' as the conventional space S' due to the conditions of the etching process. Next, the coining process is shown in FIGS. 4 and 5.

The coining process is a process in which the lead inner ends 1a, la, etc. of the lead frame A are crushed by a press or the like, and through this process, the thickness T' of the lead inner ends 1a becomes T while maintaining the pitch P. to shrink.

Furthermore, as the thickness of the inner end portion 1a of the lead is reduced to T, the width W' of the inner end portion of the lead expands to W, and the side surface bulges outward to reduce the space between the inner end portions 1a and 1a. S' is S
(Figure 5).

The thickness reduction, ie, the coining amount T'T, is set so as to obtain the width W necessary for bonding.

The upper surface of the lead inner end portion 1a serves as a bonding surface, and the bonding wire 3 connected to the semiconductor chip 2 is connected to this surface by the wire bonding method (FIG. 7).

By ensuring the predetermined width W at the lead inner end portion 1λ, the bonding work can be easily and reliably performed, and the bonding strength can also be ensured.

Although FIG. 7 shows a case in which the semiconductor chip 2 is connected to the semiconductor chip 2 by wire bonding, it is also possible to connect by bump bonding. Although a case where the lead frame A is also used as the lead frame A will be exemplified, it goes without saying that the present invention can be applied to a frame structure in which the die pad is integrally formed with the lead frame A.

(Effects) According to the present invention, the bonding surface at the inner end of the lead of the lead frame can be secured to a predetermined width, and the lead pitch at this portion can be reduced compared to when using only the conventional etching method. A lead frame that can accommodate a large number of pins can be formed, and can be used as an ultra-high-speed, high-capacity semiconductor device.

Further, since the etching process does not require any special etching method, molding is easy and inexpensive, and productivity can be increased with a high yield.

[Brief explanation of the drawing]

Fig. 1 is a plan view of the lead frame of the present invention which has been subjected to etching processing, Fig. 2 is a sectional view taken along the line (n)-(n), and Fig.
The figure is an enlarged end view taken along the line (II[)-(m) in Figure 2, Figure 4 is a sectional view corresponding to Figure 2 showing the coining process, and Figure 5 is the (V )-(V) line enlarged end view, FIG. 6 is a sectional view corresponding to FIG. 3 of a lead frame formed by the conventional method to ensure a predetermined width W, and FIG. 7 is an example of the use of the lead frame of the present invention. FIG. In the figure, A is the lead frame, 1 is the lead, 1a is the inner end of the lead, W' is the width of the etched inner end of the lead, and W is the width of the inner end of the coined lead.

Claims (1)

[Claims] 1. A method for forming a lead frame, which comprises forming the inner ends of the leads into a multi-fingered array by etching, and then applying a coining process to crush the inner ends of the leads to widen the bonding surface.