JPH0468708A - Digital filter - Google Patents

Abstract

PURPOSE:To decrease the circuit scale to economize by providing a coefficient memory with a tap coefficient corresponding to plural filters stored therein to each step, using the filter while selecting the tap coefficient and using a multiplier and an adder or the like in common to each filter. CONSTITUTION:An ADP 6 points out a 1st address of coefficient memories 2-1-2-K at first. When an input data is inputted to an IN1, multipliers MPY 3-1-3-K of each tap multiply the said input data with a tap coefficient stored in a first address of each of the coefficient memories 2-1-2-K. The result of each multiplication is added with a data stored in each of pre-stage delay registers D4-1-4-(K-1) by each of adders 5-2-5-K except the result of the multiplication of the MPY 3-1 and the result is inputted to each of the D4-2-4-K except the result of multiplication of the MPY 3-1. Moreover, the result of the multiplication of the MPY 3-1 is inputted as it is to the D4-1. The processing above indicates one cycle. Then the ADP 6 points out the end address of each of the coefficient memories 2-1-2-K.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a digital filter for performing sampling rate conversion.

(Prior Art) Fig. 2 is a diagram showing the concept of sampling rate conversion, and shows the case where a digital signal with a sampling rate of 4f (f is the sampling frequency) is converted into a digital signal with a sampling rate of 4f. be.

This sampling rate conversion creates a signal with a sampling rate of 12f by inserting (zero interpolation) two samples of "0" signals for each sample into a digital signal with a sampling rate of 4f, and converts this signal into a signal with a passband of 12f. This is achieved by passing the sample through a 3f low-pass filter (FIR type filter) and thinning out the result at a rate of one out of every four samples.

FIG. 3 is a block diagram showing an example of the configuration of the FIR filter (tap coefficient is K).

The second FIR type filter has an input register (IN) 1 that inputs input data, and a multiplier (MPY) that performs multiplication at each tap. ) 3-1 to 3-, adders 5-2 to 5- that add the multiplier output and the addition result of the previous stage at each tap, and a delay register (D) 4 that stores the addition result of the previous tap. -1 to 4-, and can perform the filter calculation shown in equation (1).

Y9: Output data X e-i: Input data Hi: Tap coefficient = Q-P+1 That is, in FIG.
) 1, at each tap, the multiplier (MPY) 3
-1 to 3-K input data to each coefficient register 6-1
Multiply the coefficients (H1 to HK) stored in ~6-K. The multiplication result of the first tap, that is, the output of MPY3-1, is input to the delay register (D) 4-1, and the multiplication result of other taps, that is, the output of MPY3-2 to MPY3-3-, is input to the adder 5-2 to 5-K allows the previous tap D4-1 to 4-(
By repeatedly performing operations such as 0 or more that are added to the data from K-1) and input to D4-2 to D4-4 of each tap, the calculation result shown in equation (1) is obtained from D4-K. It will be output.

That is, when input data is input to the input register (INI) at the same rate as the sampling rate of the input data, the FIR filter processing shown by the above equation (1) is performed, and the final stage delay register (D4- K) outputs the calculation result at the same rate as the sampling rate of the input data.

However, as mentioned above, the sampling rate is 4f.
When converting from to 3f, the operation of the FIR type filter is changed to 1
It has to be 2f. This frequency 12f is three times the sampling rate (4f) of the source signal. In the case of digital signals with very high sampling rates, such as video signal processing, the sampling rate is 3.
Operating the hardware at twice the speed had problems such as fewer usable devices and the possibility of hardware problems (ringing, etc.) due to the high speed.

One way to solve this problem is to simplify the sampling conversion procedure.
It is described in. FIG. 4 is a block diagram showing the sampling rate conversion method according to the above method, in which both the data input rate and output rate are 4f. Since the output rate is 4f instead of 3f, invalid data is output once every 4 samples. F430. F431. F4
32 is an FIR type filter having the same configuration as in FIG. 3,
The original tap coefficient is divided into three parts, and the number of taps in each filter is approximately 1/3 of the original number of taps.

Every time input data is input, the filter output switch is cyclically switched to terminals a, b, c, and d in order, and the output of each filter is output. When the switch selects terminal d to which no filter is connected, invalid data is output. Note that each filter operates at the same speed as the sampling rate (4f) of input data.

Therefore, usable devices are not limited to conventional devices.

Also, since the conventional technology is not very fast, it is difficult to design the hardware.

(Problem to be solved by the invention! I) However, in the circuit that performs the above-mentioned sampling rate conversion, it is necessary to use a plurality of FIR type filters as shown in Fig. 3, so the circuit scale becomes large and the price becomes high. There was a problem.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a digital filter for economical sampling rate conversion with a small circuit scale.

(Means for Solving the Problems) In order to achieve the above object, the present invention provides an FIR type digital filter that performs sampling rate conversion, which includes a coefficient memory that stores tap coefficients corresponding to a plurality of filters, and a coefficient memory that stores tap coefficients corresponding to a plurality of filters; a multiplier that multiplies input data by a tap coefficient output from memory; an adder that adds the multiplication result of the multiplier to data from the delay register of the previous tap; a plurality of taps consisting of a delay register that outputs with a delay of one cycle; and cyclically selecting tap coefficients from each coefficient memory in synchronization with the input data, and changing the order once for each of the plurality of taps. It is provided with an address pointer that outputs the address of the tap coefficient to each coefficient memory so as to shift the address by the tap coefficient and output it.

(Function) At each tap, the multiplier multiplies the input data by the tap coefficient output from the coefficient memory and outputs the result to the adder. The adder adds the multiplication result from the multiplier and the data from the delay register of the previous tap, and sends the result to the adder of the next tap via the delay register. Here, all data simultaneously input to the adder is the product of the number of taps corresponding to the same filter in each step and the input data, or the sum thereof. This is due to the switching of tap coefficients in each coefficient memory and the operation of the delay register. Therefore, the final output is a form in which data that has passed through a plurality of filters is sequentially output, and by setting the tap coefficient to a predetermined value, data whose sampling rate has been converted can be obtained.

(Embodiment) FIG. 1 is a block diagram showing an embodiment of the present invention, and is an example of converting the sampling rate from 4f to 3f. In Figure 1, 1 is an input register (IN) for inputting input data, 2-1 to 2- are coefficient memories that can store four tap coefficients for each tap, and 3-1 to 3- are for each tap. a multiplier (PMY) that performs multiplication at 5-
2 to 5- are adders that add the multiplier output and the previous stage addition results at each tap, 4-1 to 4- are delay registers (D) that store the addition results at each tap, and 6 is a coefficient memory. It outputs addresses from 2-1 to 2-.
The address is incremented by 1 each time input data is input, and becomes 4.
When the cycle indicating the 1st address is completed, the address pointer (ADP) is returned to the 1st address, and 7 is A
This is an address output bus that outputs the output address of DP6 to each coefficient memory 2-1 to 2-K. The output of INI is connected to the MPY3-1 to 3K(7)y'-small input of each tap, and the output of ADP6 is connected to the coefficient memory 2 of each tap.
-1 to 2- are connected to the address inputs of the coefficient memory 2.
The outputs of -1 to 2- are connected to the coefficient inputs of MPY3-1 to 3-.

The output of MPY3-1 is connected to the input of D4-1, and the output to other MPY3-2 to 3- is connected to each adder 5-2 to 5.
- is connected to one of the two inputs of the. The output to the adder 5-2 to 5- of each tap is each D4-2
~4-, each D4-1~4-(K-1
) is connected to the other input of the next tap adder 5-2 to 5-. The output of the final tap D4- is connected to the output terminal.

Next, the operation of this embodiment will be explained. in advance,
In the first tap coefficient memory 2-1, address 1
The second address has a tap coefficient (F430)+ corresponding to filter F430 shown in Figure 4, the second address has a tap coefficient (F431) corresponding to filter F431, and the third address corresponds to filter F432. tap coefficient (F432).

However, invalid tap coefficients are stored at the fourth address, and in the second tap coefficient memory 2-2,
The first address is an invalid tap coefficient, the second address is a tap coefficient (F430) t corresponding to filter F430 shown in FIG. 4, and the third address is a tap coefficient (F430) corresponding to filter F431. F431) z
However, the tap coefficient (F432) 2 corresponding to the filter F432 is input to the fourth address, and the tap coefficients are stored in each of the coefficient memories 2-3 to 2-K according to the above-described rule. FIG. 5 shows the above rules. Note that the order in which the tap coefficients are stored is the same for each tap,
The order in which the tap coefficients are read may be shifted by one address for each tap.

ADP6 initially indicates the first address of each coefficient memory 2-1 to 2-2-. When input data is input to INI, the input data is multiplied by the tap coefficient stored in the first address of each coefficient memory 2-1 to 2- in MPY 3-1 to 3- of each tap. Ru. Each multiplication result is sent to each adder 5-2 to 5- except for the multiplication result of MPY3-1.
Then, the data is added to the data stored in the previous stage D4-1 to D4-4-(K-1) and input to each D4-2 to D4-4-K.

Note that the multiplication result of MPY3-1 is inputted as is to D4-1. This is one cycle.

Next, ADP6 indicates the second address in each coefficient memory 2-1 to 2-. When the next input data is input, the input data is multiplied by the tap coefficient stored in the second address of each coefficient memory 2-1 to 2- in MPY3-1 to 3- of each tap. , each multiplication result is sent to each adder 5
-2 to 5- are added to the data stored in the previous stage D4-1 to D4-4- (K-1), respectively, and D4-2 to D4-4-
It is input to K. Note that the multiplication result of MPY3-1 is D4
-1 is input. At this time, data corresponding to the calculation results up to the second tap of the filter F430 shown in FIG. 4 is input to the second tap D4-2.

Each time input data is input, the above cycle is repeated while incrementing the address indicated by ADP6 by 1 for each cycle. When it is the fourth address, the next address becomes the first address again. In the output, the result when input data is passed through filter F430, the result when input data is passed through filter F431, the result when input data is passed through filter F432,
Invalid output data is output in sequence. In other words, the input signal with a sampling rate of 4f is the sampling rate) 3
It is converted into a f signal and output.

Note that in this embodiment, the output rate is 4f, which is the same as the input rate.
Therefore, invalid data is output once every four samples.

(Effects of the Invention) As described above in detail, according to the present invention, a coefficient memory storing tap coefficients corresponding to a plurality of filters is provided in each step, and the tap coefficients are switched and used.
Multipliers, adders, etc. are commonly used for each filter.

Therefore, the number of multipliers, adders, etc. that are large in hardware scale and expensive can be minimized, and a digital filter for economical sampling rate conversion with a small circuit scale can be obtained. .

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a conceptual diagram of sampling rate conversion, and Fig. 3 is a conventional FIR
FIG. 4 is a block diagram of a simplified sampling rate conversion method, and FIG. 5 is an explanatory diagram of a rule for inputting coefficients to a coefficient memory. 1... Input register, 2-1 to 2-K... Coefficient memory, 3-1 to 3-K... Multiplier, 4-1 to 4-K...
・Delay register, 5-2 to 5-K...Adder, 6...
・Address pointer, 7...Address output bus.

Claims (1)

[Claims] An FIR type digital filter that performs sampling rate conversion, comprising: a coefficient memory that stores tap coefficients corresponding to a plurality of filters; and a multiplier that multiplies input data by the tap coefficients output from the coefficient memory. A multiplier, an adder that adds the multiplication result of the multiplier and data from the delay register of the previous tap, and a delay register that delays the addition result of the adder by one cycle of the input data and outputs the result. a plurality of taps, and tap coefficient addresses so as to output tap coefficients in sequence from each coefficient memory in synchronization with the input data, and to shift the order by one tap coefficient for each of the plurality of taps. and an address pointer that outputs the value to each coefficient memory.