JPH0468941A - Offset control system - Google Patents

Abstract

PURPOSE:To reduce deterioration in a bit error rate by dividing sampling values of the amplitude of a base band signal before identification into positive and negative values, collecting them depending on the polarity, averaging them, obtaining an offset based on a difference between the positive average value and the negative average value and superimposing the offset onto the base band signal. CONSTITUTION:The system is provided with an identifier device 1 using a recovered clock recovered from an inputted base band signal so as to extract an identification data of the base band signal and with a 1st hold means 2 holding the amplitude of the base band signal inputted in a timing of the recovered clock. Moreover, the system is provided with a 2nd hold means 3 holding the amplitude of the inputted base band signal when the identification data has other prescribed polarity, and a control voltage generating means 4 averaging outputs of the 1st and 2nd hold means 2, 3 and adding the averaged outputs to generate a control voltage. Then an offset is eliminated by superimposing the control voltage onto the inputted base band signal. Thus, the deterioration in the bit error rate due to the offset generated by a temperature change or a secular change of components in use is reduced.

Description

[Detailed Description of the Invention] [Summary] For example, regarding an offset control method used in a demodulator that demodulates PSK, 4-phase PSK, or FSK modulated waves, bits due to offsets caused by temperature changes or changes in used parts over time, etc. The aim is to minimize the degradation of the error rate, and when a discriminator identifies the baseband signal using a regenerated clock regenerated from the input baseband signal and extracts the identification data, the identification data is At the time of polarity, at the timing of the regenerated clock.

The first one holds the amplitude of the input baseband signal.
holding means, and when the identification data has a different predetermined polarity,
a second holding means for holding the amplitude of the input baseband signal at the timing of the reproduced clock; A control voltage generating means for generating a control voltage by averaging and adding the outputs of the second holding means is provided, and the control voltage is superimposed on the input baseband signal to remove an offset.

[Industrial application field]

The present invention can be applied to, for example, PSK, 4-phase PSK or FSK.
This invention relates to an offset control method used in a demodulator that demodulates a modulated wave.

For example, if an offset voltage occurs at the input of a multilevel GAM demodulator due to temperature changes or aging of used components, the bit error rate will deteriorate and the line quality will deteriorate.

Therefore, it is necessary to minimize the deterioration of the bit error rate due to offsets caused by temperature changes or changes in the parts used over time.

[Conventional technology]

FIG. 4 is a block diagram of a conventional example, and FIG. 5 is an explanatory diagram of the operation of FIG. 4. The operation shown in FIG. 4 will be explained below with reference to FIG.

First, the demodulated baseband signal is applied to the discriminator 11 via the adder 15. The discriminator 11 uses the reproduced clock to discriminate at the maximum aperture portion of the eye pattern (discrimination point in the figure) as shown in FIG.

As a result, the above baseband signal is converted into a digital signal and sent to the outside as identification data, but a portion is added to the window comparator 12.

The window comparator has a first threshold value v1 and a second threshold value V, and the converted digital signal has a first threshold value v1 and a second threshold value V1.
It is checked whether it is between the second threshold values V,, V,.

As shown in FIG. 5, for example, in the case of a baseband signal without offset (eye pattern E), the identification voltage is the first
．． Since the voltage is between the second thresholds V, , V, the window comparator 12 determines that there is no offset and outputs the output voltage V to the amplifier 13 . It is superimposed on the baseband signal via a loop filter composed of a low-pass filter 14 and an adder 15.

At this time, since the eye pattern is within the window, the output of the window comparator is constant, and no control is performed to remove the offset.

However, in the case of a baseband signal with an offset (eye pattern E2), the identification voltage is thicker than the first threshold v1 (so the window comparator 12 loops the output voltage (vo-ΔV), for example. Control is performed to compress the offset ΔV in addition to the adder 15 via a filter.

Here, the above-mentioned offset occurs due to temperature changes or changes in the parts used over time, but it changes slowly. Furthermore, when the offset is in the opposite direction to the above, (V6+ΔV) is added to the adder I5 to compress the offset.

As a result, the dotted line eye pattern in FIG. 5 becomes like the solid line eye pattern, and the eye pattern falls within the window.

[Problem to be solved by the invention]

Here, the offset that occurs in the transmitter or receiver is a factor that degrades the bit error rate when identifying reproduced data, but when the amplitude of the baseband signal input to the discriminator is small (1) growing.

For example, in the case of the eye pattern indicated by the dotted line in FIG. As the area becomes narrower, the lower part becomes even narrower, and the effect becomes particularly large. In addition, the offset is −Δ
When it is V, the margin in the upper part decreases.

That is, there is a problem in that the bit error rate deteriorates due to offsets caused by changes in temperature or changes in components used over time.

(Means for solving problems) FIG. 1 shows a block diagram of the principle of the present invention.

In the figure, 1 is a discriminator that identifies the baseband signal and extracts identification data using a regenerated clock that is regenerated from a manually generated baseband signal, and 2 is a discriminator that extracts identification data by using a regenerated clock that is regenerated from a manually generated baseband signal. This is a first holding means that holds the amplitude of the baseband signal inputted at the timing.

Further, 3 is a second holding means for holding the amplitude of the baseband signal inputted at the timing of the reproduction clock when the identification data has another predetermined polarity, and 4 is the first holding means. This control voltage generation means generates a control voltage by averaging and adding the outputs of the second hold means.

Then, the offset is removed by superimposing the control voltage on the input baseband signal.

[Effect]

In the present invention, sampling values obtained by sampling the amplitude of the baseband signal before identification are collected separately on the positive side and the negative side and averaged. Then, the offset is determined by taking the difference between the positive average value and the negative average value.

That is, the discriminator discriminates the input baseband signal using the reproduced clock and outputs the discrimination result.

The first holding means inputs and holds the amplitude of the discrimination point of the baseband signal before discrimination when the discrimination result is 1.

Further, when the identification result is O, the second holding means inputs and holds the amplitude of the identification point of the baseband signal before identification.

Then, the control voltage generating means averages and adds up the amplitudes held in the two holding means, and the result of the addition becomes an offset voltage.

When this addition result is superimposed on the baseband signal, the offset is removed, thereby eliminating deterioration of the bit error rate due to the offset.

〔Example〕

FIG. 2 is a block diagram of an embodiment of the present invention, and FIG. 3 is an explanatory diagram of the operation of FIG. 2.

Here, the symbols on the left side of FIG. 2 indicate the waveforms of the portions with the same symbols in FIG. In addition, the inverter 21° switch 22
, the hold portion 23 is a component of the first hold means 2, and the switch 31 . The hold part 32 is a component of the second hold means 3, low-pass filters 41, 42 . Adders 43 and 44 are components of the control flI voltage generation means 4. Note that the same reference numerals indicate the same objects throughout the figures.

The operation shown in FIG. 2 will be explained below with reference to FIG. still,
It is assumed that the recovered clock is extracted from the input bass punt signal in a separate section and supplied to the identification section of FIG.

First, a baseband signal as shown in FIG. The discriminator is shown in Figure 3-■
As shown in FIG. 9, the above baseband signal is identified at, for example, the rising point of the recovered clock, and identification data of 1 or 0 is output.

Further, it is assumed that the switch 22 to which the inverter 21 is attached is turned on (the state shown by the dotted line) when the identification data is 1, and the switch 31 is turned on (the state shown by the solid line) when the identification data is 0.

Now, since the switch 22 is in the on state at the point of the reproduced clock a, the amplitude v3 of the discrimination point of the baseband signal before discrimination is held in the hold part 23 via the switch 22 (Fig. (See left part).

At the point of the reproduced clock b, the switch 31 is turned on, and the amplitude (4) of the discrimination point of the baseband signal before discrimination is held in the hold portion 32 via the third switch. Since the identification data at the point of the reproduced clock C is also 0, the switch 31 is turned on again and the amplitude v4 is held in the hold portion 32.

Next, at the point of the reproduced clock d, the amplitude of the baseband signal at the discrimination point is held in the hold portion 23, but at this time it is a value that is ΔV lower than the previous hold value.

Also, at the point of the reproduced clock e, the amplitude of the baseband signal at the identification point is held in the hold portion 32, but at this time it becomes a value larger than the previous hold value by Δv4 (
(See the center part of Figure 3 - ■, ■).

Thereafter, the above operation is repeated to obtain the reproduced clock f.

The corresponding amplitudes of the baseband signals at points i, j are held in the hold section 23, and the recovered clock g.

At point h, the corresponding amplitude of the baseband signal is held in the hold portion 32, and as a result, as shown in FIG.

The hold value shown in (2) is obtained. Incidentally, the hold portion is composed of a capacitor as is well known.

Then, when the output of the hold portion 23 is averaged by four low-pass filters, the average value of the input to the discriminator when the discrimination data is 1 is obtained as shown in FIG. Similarly, the fifth
As shown in Figure-■, the average value when the identification data is O is obtained.

An offset voltage is obtained by adding these average values in an adder 43, so by superimposing the output of the adder 43 on the baseband signal in an adder 44 as a control voltage,
Offsets can be removed.

In other words, deterioration in the bit error rate can be reduced by automatically removing DC offsets (due to temperature changes or aging of used parts) that occur in the baseband signal.

〔Effect of the invention〕

As described in detail above, according to the present invention, it is possible to minimize the deterioration of the bit error rate due to offsets caused by temperature changes or aging of used parts.

[Brief explanation of drawings]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram of an embodiment of the invention, Fig. 3 is an explanatory diagram of the operation of Fig. 2, Fig. 4 is a block diagram of a conventional example, and Fig. 5 is a block diagram of an embodiment of the present invention. The operation explanatory diagram of FIG. 4 is shown. In the figure, 1 is a discriminator, 2 is a first holding means, 3 is a second holding means, and 4 is a control voltage generating means. 1 principle of the present invention 1 B ■ 〇- ? -22F≧]/) Death BF4313 with seed kui Figure 4-Zen T4 I1/) Su〃 work A is BF4U

Claims (1)

[Claims] When the discriminator (1) identifies the baseband signal and extracts the identification data using a regenerated clock regenerated from the input baseband signal, when the identification data has a predetermined polarity, a first holding means (2) for holding the amplitude of the input baseband signal at the timing of the reproduction clock; and a first holding means (2) for holding the amplitude of the input baseband signal at the timing of the reproduction clock; A second hold means (3) for holding the amplitude of the band signal, and a control voltage generation means (4) for generating a control voltage by averaging and adding the outputs of the first and second hold means, An offset control method characterized in that the offset is removed by superimposing the control voltage on the input baseband signal.