JPH0469736A - Microprogram controller - Google Patents

Abstract

PURPOSE:To improve the evaluation efficiency by providing a ROM for storing a microprogram, and a RAM which is used as an address trace memory of the microprogram at the time of regular operation, and used as a means for storing an evaluation microprogram at the time of evaluation. CONSTITUTION:A ROM 1 stores a microprogram, and a RAM 2 is used as a means for storing the microprogram at the time of evaluation of the microprogram, and used as an address tracer at the time of regular operation. In such a state, when the housing of the microprogram to the RAM 2 is finished, a microprogram address 103 from a selective circuit 3 is selected by a selecting circuit 6 and supplied as a microprogram address 105 to the RAM 2, and by selecting output data 204 from the RAM 2 by a selective circuit 7, the initial evaluation of the microprogram is executed. In such a manner, the initial evaluation of the microprogram, the evaluation can be executed, while rewriting the data of the RAM 2, the evaluation can be simplified and the evaluation efficiency can be improved.

Description

[Detailed description of the invention] Technical field The present invention relates to a microprogram controller.

BACKGROUND TECHNOLOGY Conventionally, in a microprogram control device, as shown in FIG.
Then, one of the branch address 101 specified from the outside and the branch address 102 specified by the microinstruction held in the microinstruction register 8 is selected, and that address is stored in the memory circuit]0 as the microprogram address 103. Supplied.

Microprogram address 1, 03 from selection circuit 3
The microinstruction 302 read out from the storage circuit 10 by
is held in the microinstruction register 8 and then supplied to another circuit (not shown) as a microinstruction 303.

The read operation from the memory circuit 10 described above performs a normal operation for executing the microprogram stored in the memory circuit 10 and an evaluation operation for evaluating the microprogram.

In addition, the tQ circuit 10 or ROM (read only memory)
In the case of
In this case, the write data 301 is written using the microprogram address 103 from the selection circuit 3.

In such a conventional microprogram control device, a ROM is used as a memory circuit 10 for storing microprograms.
Or, since only RA and M were used, memory circuit 1
When using ROM with 0 and ]7, the contents cannot be easily rewritten when changing the microprogram, and the
Since it is necessary to replace M, there is a problem that evaluation efficiency deteriorates.

Furthermore, when a RAM is used as the memory circuit 10, the contents can be easily rewritten when changing the microprogram, but the microprogram must be written during the initial setup of the device, which reduces the initial setup time of the device. This was one of the hindering factors.

Purpose of the Invention The present invention has been made to eliminate the problems of the conventional ones as described above, and can improve evaluation efficiency.
The proposal of a microprogram control device that can shorten the initial setting time of the device is defined as CJ (1-1).

Composition of the Invention A micro program control device according to the present invention includes a read-only memory for storing a micro program, a memory that can be freely written to and read from, and a memory that can be freely written to and read from continuously, and a memory that is stored in the read-only memory during normal operation. The microprogram is characterized by comprising a control means that operates as a trace memory for storing an address when executing the microprogram, and a control means for controlling the microprogram to operate as a storage means for storing an evaluation microprogram at the time of evaluation.

Embodiment Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, ROMI stores a microprogram, and RAM2 is used as a means for storing the microprogram when evaluating the microprogram, and is used as an address laser during normal operation.

The selection circuit 3 uses a counter 9 to sequentially increase the power 10? Select one of the address 104 from the address register 4 to be executed, the branch address +01 specified from the outside, and the branch address 102 specified by the microinstruction stored in the microinstruction register 8. Microprogram address 103 during normal operation
to ROMI (!().

Address register 4 holds the address to ROM1,
This held address is sequentially incremented by 1 by the counter 9.

The selection circuit 5 selects the write data 202 specified from the outside during evaluation, and selects the write data 202 from the selection circuit 3 during normal operation.
It selects microprogram address 1.03 supplied to , and sends the selected data to RAM 2 as write data 203 .

The selection circuit 6 selects the microprogram address 103 supplied from the selection circuit 3 to the ROM 1 during evaluation, selects address 04 from the address register 4 which is sequentially incremented by ] by the counter 9 during normal operation, and selects the address RAM as microprogram address 105
Supply to 2.

The selection circuit 7 selects the output data 2 from the ROMI during normal operation.
Select 0+ and output data 20 from RAM2 during evaluation.
4 is selected and the data is sent to the microinstruction register 8 as a microinstruction 205.

The microinstruction register 8 holds the microinstruction 205 from the selection circuit 7, and stores the contents as the microinstruction 206.
At the same time, the branch address 102 specified by the held content is sent to the selection circuit 3 as 111.

Note that the selection circuits 3, 5 to 7 each perform a selection operation in response to an external Moto signal.

The operation of one embodiment of the present invention will be explained using FIG.

When evaluating a microprogram, the RAM 2 is used as a memory to store the microprogram, so address data is first set in the address register 4 by a scan operation, and the address 104 from the address register 4 is selected by the selection circuit 6. and supplies it to R, A M 2 as the microprogram address 105.

Further, the selection circuit 5 selects write data 202 specified from the outside, and R
By sending the data to A M2, the evaluation microprogera l is written to RAM M2.

By repeating the operations described in section 2 above, all microblocks for evaluation are stored in the RAM 2.

When the storage of the microprogram in the RAM 2 is completed, the selection circuit 6 selects the microprogram address 103 from the selection circuit 3 and supplies it to the RAM 2 as the microprogram address 105, and the selection circuit 7 selects the microprogram address 103 from the selection circuit 3.
By selecting the output data 204 from M2, the rewritable RA M2 is used as a memory to store the microprogram to perform an initial evaluation of the microprogram.

On the other hand, during normal operation, RAM2 is used to store the evaluated microprogram in ROMI, and
Since M1 is used as a memory for storing a microprogram, and at the same time RAM2 is used as an address tracer for a microprogram read from ROMI and executed, the microprogram address 103 from the selection circuit 3 is supplied to ROMI, ROM1 with selection circuit 7
By selecting the output data 201 from ROM
The microprogram read from 1 is executed.

At this time, the address 104 from the address register 4 selected by the selection circuit 6 is supplied to RA, M2 (jtH), and the selection circuit 5 reads out the microprogram address 103 from the selection circuit 3, that is, from the ROM 1. Since the address of the microprogram executed by the microprogram is selected as the write data 203, the R
The address of the microprogram read from OMI and executed is written.

Therefore, RAM2 can be used as an address tracer for a microprogram read from ROMI and executed.

RA, M2 (when reading the stored microprogram address when a failure occurs, stop the microinstruction + L to stop the clock), select circuit 7 selects RA
After selecting the output data 204 from M2, a total of 7111 portions of RAM 2 are sequentially read out by repeating one clock step operation to detect a failure in the device.

In this way, the ROMI used as memory for storing microprograms and the address tray during normal operation →
By providing RAM2, which is used as a memory to store the evaluation microprogram at the time of evaluation, it is possible to perform evaluation while rewriting the data in RAM2 during the initial evaluation of the microprogram. , it is possible to simplify the evaluation and improve the evaluation efficiency.

In addition, since the microprogram write operation at the time of initial setting is unnecessary during the initial setting of the device during normal operation,
The time required for initial setting of the device can be reduced.

Conventionally, when only ROM or RAM was used, only one of the effects described in L could be obtained, but in this embodiment, both effects can be obtained at the same time.

Furthermore, address tracing at the time of a failure can be performed simply by operating without reading the contents of the RAM 2, so that address tracing can be easily performed.

Effects of the Invention (2) According to the present invention, there is a ROM for storing a microprogram, a ROM that is used as an address I/race memory for the microprogram during normal operation, and a means for storing an evaluation microprogram during evaluation. By providing a RAM to be used, evaluation efficiency can be improved and the initial setting time of the device can be shortened.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 2 is a block diagram showing the configuration of a conventional example. Explanation of symbols of main parts 1... ROM 2... RAM 3゜5~7... Selection circuit 4... Address register 8... Micro instruction register output 1 Jinkofuto 1 Electric Co., Ltd. 1

Claims (1)

[Claims] (1) A read-only memory for storing a microprogram, a readable and writable memory, and an address for executing the microprogram stored in the read-only memory during normal operation of the readable and writable memory. 1. A microprogram control device comprising: control means for controlling the device to operate as a trace memory and as a storage means for storing an evaluation microprogram at the time of evaluation.