JPH0470115A - Pulse period identification circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a pulse period identification circuit for identifying two types of pulses with different periods.

2. Description of the Related Art Conventionally, two types of input pulses having different periods are identified using a configuration as shown in FIG. In Figure 2, 1
1 is an input terminal, into which an input pulse for identification is input. 12
is a monostable multivibrator (hereinafter abbreviated as monomulti), which receives an input pulse from the input terminal 11 and identifies it.
A pulse with a pulse width set by the values of the resistor and capacitor of the CR time constant circuit 13 is output. 14 is mono multi,
It receives the output signal of the monomulti 12 in the previous stage, holds an identification signal corresponding to the input pulse, and outputs a pulse with a pulse width set by the resistance and capacitor values of the CR time constant circuit 15 to the output terminal 16.

Problem to be Solved by the Invention By the way, in such a configuration, the output pulse width tw of the monomulti 12 is equal to the period T of each of the two types of input pulses.
l, T2 (TI<T2), T1 x TW x T2
The CR time constant of the CR time constant circuit 13 needs to be set so as to satisfy the relationship (1). However, in reality, unlike equation (1), there are cases where TI<72<TW (2) or TW<Tl<12 (3). This is a malfunction when the time constant setting of the monomulti 12 is incomplete, but if the difference between T1 and T2 is small, it may actually occur due to variations in the CR time constant of the CR time constant circuit 13, temperature drift, etc. It is very difficult to set TW.

The present invention is based on the above-mentioned problem, and an object of the present invention is to provide a pulse period identification circuit which has a simple configuration and can eliminate the drawbacks.

Means for Solving the Problems In order to solve the above problems, the pulse period identification circuit of the present invention counts inter-pulse clocks using an X-ary counting circuit when identifying two types of pulses with different periods. This method is characterized in that when the number of inter-pulse clocks is divided by X, the remainder Y is obtained and identified by Y.

Effect of the Invention With the above-described configuration, the number of inter-pulse clocks can be easily identified by the remainder Y of xtJ+1 by using an X-ary counting circuit, and therefore the scale of the counting circuit can be reduced. , the circuit configuration can be simplified. Moreover, unlike the conventional case, a time constant circuit is not required, so malfunctions due to constant variations that occur in the conventional case do not occur.

Example Below, regarding a pulse period identification circuit according to an example of the present invention,
This will be explained with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a pulse period identification circuit in one embodiment of the present invention. In FIG. 1, 1 is an input terminal to which an input pulse is applied, and 2 is a clock terminal to which a clock having a shorter period than the input pulse is applied. 3 is a flip-flop (hereinafter referred to as FF) that constitutes the input circuit, and the input pulse from input terminal 1 is applied to the D input.
A clock from clock end 2 is applied to the CK input.

4 is a counting circuit consisting of an X-ary counter, to which the clock from the CK large input clock terminal 2 is applied via the inverter 8, and is input to the CLR input via the Q output of FF3 or the inverter 9; By controlling the reset by the latched signal, the clocks between input pulses are counted, thereby obtaining a remainder Y when the number of clocks between pulses is divided by a constant X, and this is used as a signal corresponding to the input pulse. and(
7, and is usually constructed using a sequential circuit. 5 is a decoder, which outputs the remainder Y from the counting circuit 4.
is input and output as an identification signal according to the input pulse, and is usually constructed using a logic circuit, but this also includes cases in which the output of the counting circuit 4 is used as is as an identification signal in some cases.

Reference numeral 6 denotes an FF constituting a memory circuit, which holds the identification signal using the signal latched by the FF 3 as a clock and outputs it to the output terminal 7.

The input pulse inputted from input terminal 1 to FF3 is latched by FF3 by the clock inputted from clock terminal 2 to FF3, and the counting circuit is reset between the input pulses by controlling the reset by the signal latched by FF3. Count tarotsuku.

At this time, the X-ary counting circuit 4 uses a constant X as a divisor for the counted value of the pulse interval by the clock, performs a carry, and outputs the remaining remainder Y. The decoder 5 receives the remainder Y output from the counting circuit 4 and outputs an identification signal according to the input pulse. At this time, the case where the output of the counting circuit 4 is used as it is as an identification signal is also included. This identification signal is applied to the FF using the signal latched by FF3 as a clock.
6 and output from the output end 7.

Effects of the Invention As described above, according to the present invention, it is easy to design because there is no need to take element variations into account as in the conventional case that requires a CR time constant circuit, and it is stable against temperature changes and power supply voltage fluctuations. It is. Furthermore, the scale of the counting circuit is minimal and can be achieved with a simple circuit configuration.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a pulse period identification circuit according to an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional pulse period identification circuit. 1...Input end, 2...Clock end, 3...FF,
4... Counting circuit, 5... Decoder, 6... FF0
Agent Yoshihiro Morimoto

Claims (1)

[Claims] 1. An input circuit that latches the input pulse, and a clock that counts the pulse interval of the input pulse with a shorter period than the input pulse, and reset is controlled by the output signal latched by the input circuit, and there are two types with different periods. an X-adic counting circuit that outputs a remainder Y obtained by dividing the counted value of the pulse interval of the input pulses by a constant X, and an identification signal corresponding to the input pulse that receives the output signal of the counting circuit. A pulse period identification circuit comprising a theoretical circuit for outputting and a storage circuit for holding the identification signal.