JPH0470825B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a video tape recorder (VTR).
The present invention relates to techniques for modifying a video signal such that the video signal cannot be properly recorded on a video signal recorder such as a video signal recorder, but allows playback of the video signal on a conventional television receiver.

In the prior art, it has been proposed in some respects to modify the video signal so that it cannot be properly recorded by modifying the vertical blanking interval. For example, in U.S. Pat. No. 3,963,865,
All but 1.5 pulses of vertical sync pulses in vertical blanking are removed. Although the remaining 1.5 sync pulses are sufficient for proper operation of a television receiver, conventional VTRs
is insufficient for proper operation. In US Pat. No. 4,100,575, this vertical blanking interval is modified by replacing several vertical sync pulses and subsequent equalization pulses with simulated equalization pulses.

However, in the configuration of these conventional technologies,
Find the modified vertical blanking interval and
It is relatively easy to replace this with a locally generated standard vertical blanking interval, thereby allowing unauthorized recording and/or playback of the video signal.

It is therefore an object of the present invention to provide a method for modifying a video signal so that it cannot be properly recorded, the method not being easy to override the effects of the inability to properly record. It is to provide.

According to an aspect of the invention, the number of video lines included in a field of a video signal is selectively varied to obtain a modified video signal with variable field length and provided to a video receiver. , there is provided a video signal modification method characterized in that the modified video signal cannot be appropriately recorded on the video receiving side.

Modified video signals with variable field lengths cannot be recorded on conventional VTRs because they rely for their operation on the standard constant field length of the video signal to be recorded. However, the variable field length of this modified video signal does not significantly affect normal television reception and viewing. In this way, the modified video signal can be recorded and broadcast without fear of duplication.

That is, in a television receiver, even a video signal whose field length has been changed can be reproduced without being affected significantly for the following reason.

First, an image with a field in which the number of video lines has been changed will produce an affected image due to the removal or addition of lines, but this effect is slight and tolerable.

Also, in this preferred embodiment, a video line is removed or added at the end of the field. If a video line is removed or added at the end of a field, a line is removed or added at the bottom of the reproduced image. A general television receiver is designed to display an area narrower than the effective image area of the video signal, and images formed by video lines located at the ends of the field are not displayed. Therefore, if a video line is removed or added at the end of a field as described above, this has no effect on the image.

Second, there may be jitter (ie, uneasy jitter) in the image in the relationship between the video line, the removed or added field, and the adjacent field.

However, this jitter is usually tolerable.

Furthermore, by gradually changing the field length, jittering can be suppressed to a negligible level.

On the other hand, for example, in a VTR, a video signal including a field in which the number of video lines is changed cannot be properly recorded for the following reasons.

When using a VTR, recording of signals onto videotape must be performed according to a predetermined recording format.

In a VTR, a magnetic head is rotated in synchronization with a vertical sync pulse, and by moving the video tape relative to the magnetic head,
For example, one field and a vertical blanking period signal including a vertical synchronization pulse are sent one after another as one magnetic track. For this reason, if the field length is corrected, the signal cannot be recorded in a predetermined recording format.

Thus, the modified video signal modified by the method of the present invention cannot be recorded in accordance with a predetermined recording format. If a recording that does not conform to a predetermined recording format is played back, an appropriate video cannot be obtained.

As described above, according to the present invention, in a television receiver, images can be properly reproduced without being significantly affected by the video signal as described above, but in a VTR, The video signal as described above cannot be recorded properly.

As mentioned above, preferably the field length of the video signal is varied, for example, by removing lines or repeatedly adding lines at the end of individual fields of the video signal. To prevent image jitter in conventional television reception of broadcast modified video signals, the field lengths of the video signals are changed at a rate of not more than one line per three fields on average. desirable.

To facilitate playback of the modified video signal, changing the field length of the video signal such that the long-term average value of the field length of the modified video signal is equal to the field length of the unmodified video signal. is desirable.

In the embodiments of the invention described in detail in the text below, the step of changing the field length of a video signal includes recording a video signal line of the video signal to be successively modified in memory and reading this line from memory. The lines are read out substantially sequentially, but lines are removed from the end of each field to produce each shortened and expanded field in the modified video signal, or read out twice. It will be done.

For example, the received modified video signal
It is conceivable to provide a receiving station decoder in order to convert it back into a fixed field length video signal that can be recorded on a VTR.
However, such decoders are usually too expensive and impractical to equip at the receiving station.

Embodiments of the present invention will be described in detail below with reference to the drawings.

In FIG. 1, a video signal from a program source 10 is modified by a video signal encoder 11, and the resulting modified video signal and audio signal from the program source are provided to a transmission system 12 for broadcast. A TV transmission system is shown. To maintain the timing of the transmitted audio signal consistent with the average timing of the audio signal path or modified video signal from the program source 10 to the transmission system 12, an amount of signal delay of, for example, 30 ms (one A delay device (not shown) may also be included to provide the duration of the television field. Broadcast signals are broadcast as shown via cable 13, but alternatively these signals can be provided by electromagnetic waves, either directly or via a satellite link. As shown, the broadcast signal is optionally provided via a conventional channel converter 14 to a conventional television receiver 15 for reproduction in a manner well known in the art.

As will be explained in detail below, video signal encoder 11 performs modification of the video signal by providing variable field lengths to the video signal. The change in field length is provided to the television receiver 15.

As will be explained in detail below, video signal encoder 11 performs modification of the video signal by providing variable field lengths to the video signal. The change in field length is insufficient to adversely affect the normal playback of the TV signal by the television receiver 15, and is not noticeable in normal viewing, for example in a video tape recorder. This interferes with the recording of video signals.

FIG. 2 shows a block diagram of video signal encoder 11. Video input signal from program source 10 is 4.2MHz vs. signal low pass filter 2
00 to the inputs of timing extractor 201 and analog/digital (A/D) converter and latch 202.

The A/D converter samples the analog video signal provided by the timing extractor 201 at a frequency fs equal to four times the color subcarrier frequency fb of the video signal and converts each sample into an 8-bit signal stored in a latch. Convert linearly to digital numbers. This allows the color
Subcarrier frequency fb is 3.579545MHz
An NTSC video signal provides 910 digital samples per horizontal line. These digital samples are written to memory 203 under the control of control circuit 204 from which they are later read. The digital samples read from memory 203 are provided to a latch and digital-to-analog converter 207, which operates at frequency fs to latch the provided digital value and convert it into an analog video signal. Convert to signal. This analog video signal is filtered and equalized in a 4.2 MHz low pass filter and a (sin x)/x equalizer, shown as a single block 208 whose output constitutes a modified video output signal. Timing extraction device 201 supplies various timing signals to memories 203 and 204 and a signal fs to devices 202 and 207.

Timing extraction device 201 is shown in more detail in FIG. Color burst extraction device 30
0 is the name of the input video signal, from the horizontal line to the color
The burst is extracted and fed into a color burst phase-locked loop (PLL) 301, which reproduces the color burst frequency fb. This includes yet another oscillator with a frequency of 40 fd.
PLL, the output of which is divided to produce various frequency signals shown in FIG. 3 and discussed below. This another PLL
and the frequency divider are shown as a single block 302. Synchronize the input video signal with separator 30
3, which derives a composite sync signal from the video signal and triggers a line counter 304 to count the horizontal lines of each field.

The output signal ff of line counter 304, which is a logical 0 in each vertical interval, produces a signal O/E that changes the state of each field divided by field counter 305, whose state is thus corresponds to the phase of the color burst of the input video signal. counters 304 and 3
05 is the signal f generated in block 302 and having 10 times the color subcarrier frequency fb.
synchronized by Block 302 also receives the signal fs = 4fb, which has already been described, and the frequency fs = 1/1
3, a signal fh having a horizontal line frequency and a signal fh, which also has a horizontal line frequency, and which has a logical value of 0 at each horizontal line period pulse of the video signal.
The various timing signals thus have frequencies as follows. That is, f=35.79545MHz fh==15.734KHz fs=14.31818MHz ff=59.94Hz fl=1.1014MHz O/E=29.97Hz FIG. 4 shows the memory 203 in more detail.

This memory consists of 104 TTL 64 Mbit RAMs with associated TTL/ECL and ECL/TTL converters as shown in block 400.
(Random access memory). this
The RAM was periodically controlled and addressed by address and control signals provided by control circuit 204 for writing and reading digital video signals. Each memory access
Due to the relatively slow speed of the cycle, digital
The video signal is divided into 13 8-bit words at a time.
written and read with respect to RAM, 10
One bit of each word is written to or read from each of the four RAMs. Therefore, the signal
A/D converter and latch 20 under the control of fs
The 8-bit video signal words from 2 are transferred to shift register 401 and the words are transferred 13 at a time to latch 402 and written to RAM under control of signal fl. Conversely, 8-bit words are read from the RAM under the control of control circuit 204 and stored 13 at a time in output latch 403 to output the signal.
input from latch 403 into shift register 404 in parallel under the control of fs to constitute the modified digital video output of memory 203. The number of 13 words written to and read from the RAM is selected with respect to the speed of the RAM and the number of 910 samples per horizontal line of the video signal;
This provides a convenient number of memory access cycles of 70 for each horizontal line.

Control circuit 204 is shown in FIG. This control circuit 204 includes a modi-euro 65 type counter 501 and a PROM 502 for generation of a control signal and selection of an address signal by the address selector 504 for each memory access cycle.
latch 503. Counter 501 is clocked by signal f to increment its count, and for each count PROM 502 is addressed to produce a set of control signals which are latched by latch 503 under control of signal f. The control signal in latch 503 is
(block 400) and memory latch 403
Write address from bus 505 or bus 50 to provide periodic operation of and RAM
Controls the selection of read addresses from 6.

The write address on bus 505 is signal fl
A 16-bit synchronous counter 5 clocked by
07, resulting in an input video signal
Words are periodically written to successive memory locations. The read address on bus 506 is generated by adding the offset selected by selector 509 from latch 510 or latch 511 to the current write address in module ²¹⁶ adder 508, and this sum is It is latched in latch 512 under control. Selector 509 is controlled by a signal "SELECT" produced at the Q output of D-type flip-flop 513, which is also provided by microprocessor 514. Microprocessor 514 supplies this offset to latches 510 and 511 and transfers it to common bus 51 under control of each latch's load signal on circuit 517.
6 provides the read address to latch 515. The microprocessor also outputs the signal N/ to the data input D of flip-flop 513.
give against. Comparator 518 is bus 50
The read address on flip-flop 513 is compared with the read address stored in latch 515, and if the compared addresses are the same, it produces an output signal gated by the signal at AND gate 519, which clocks the clock input CK of flip-flop 513.
and generates a signal EQ which is provided to microprocessor 514 as an interrupt signal.
Microprocessor 514 or latch 520
is given the starting address of the vertical interval from , which is present at the beginning of the vertical interval of the video signal, and which is applied to latch 52 under control of signal ff.
Write address on bus 505 latched at 0.

Control circuit 204 also includes a random noise source 521 and a flip-flop 522. A random noise signal, such as the noise voltage of a diode or resistor comprising source 521, is clocked by signal fh to the Q output of flip-flop 522, which output is provided to microprocessor 514.

Control circuit 204 operates as follows. As previously discussed, input video signal words are written to memory periodically and the starting address for each vertical interval is stored in latch 520. The reading of the video signal words from memory occurs approximately sequentially after some delay or offset, the amount of which is determined by the signal SELECT from one of latches 510 and 511 to adder 50.
8, in which case the selected offset amount is added to the write address to generate the read address. Each offset amount is an integer multiple of 70 so that the video signal line is read from memory a total number of line periods after being written to memory.

From each vertically spaced starting address obtained from latch 520, microprocessor 514 determines the read address at which the offset is to be changed and stores this read address in latch 515, as will be explained in more detail below. It also determines the appropriate offset and stores it in the one of latches 510 and 511 that is not selected by selector 509 at the time. With successive reads from memory, comparator 518 eventually detects the identity of the current read address generated by latch 512 and the read address stored in latch 515, and in response, signal EQ is activated. becomes 1, and then becomes 0 again when the next trailing edge of signal fl is applied to gate 519. signal
This 1-to-0 state transition of EQ triggers flip-flop 513 via its clock input CK to transfer the logic level of signal N/ at its D input to its Q output, thereby changing the logic level of signal SELECT. The offset stored in latch 510 or 511 that has been changed and was not previously selected is selected by selector 509. signal
A state transition of EQ from 1 to 0 causes an interrupt to microprocessor 514.

In response to this interrupt, the microprocessor 5
14 reads the new state of the signal select, and latches the new read address determined by this.
15, setting the signal N/ to the opposite state of the signal select. Latch 5
This new address latched at 15 is different from the current read address, so comparator 518 no longer detects an identity and signal EQ remains at zero.

Microprocessor 514 controls latch 5 to obtain the desired change in field length of the video signal.
10 and 511 and the read address for latch 515.

The direction of each change in field length, ie, whether the field is shortened or lengthened, is determined by the output of flip-flop 522.
This change in field length is done by unreading or rereading the last, e.g. 2 or 4 lines of a particular field, so that the field in the modified video signal is 2 or 4 each
Only lines are shortened or lengthened. per frame
The incremental changes in the field length of the thus obtained modified video signal, within the constraints imposed by memory size while maintaining the long-term average value of 525 television lines, are: There is no adverse effect on the reproduction of television images from the modified video signal by conventional television receivers. The variable field length results in the removal or repetition of lines at the bottom of the reproduced image, which
Since typical television receivers are configured to overscan a few lines, this is not significant and usually goes unnoticed. To avoid unpleasant image jitter due to variable field lengths, microprocessor 514 is configured to vary the field lengths relatively slowly. changing the length of one frame (two fields) by two lines so that there are at least two frames between the changes;
To cause image jitter to be subjectively negligible. In other words, the average field length change typically is no more than one lie per three fields.

The operation of control circuit 204 will be described below with reference to the flowchart in FIG. 6, by way of example. For example, assume the signal SELECT=1 to read a particular field from memory using the offset contained in latch 510. Having the conventionally known 262.5 lines, therefore,
Suppose that microprocessor 514 previously stored in latch 515 the starting address of the next field's vertical interval obtained from latch 520 and stored this offset in latch 511 for inclusion in latch 510. Further assume that the microprocessor has already determined the starting address of the next field vertical interval from latch 520 and read the output of flip-flop 522 and signal O/.

The latter signal is provided to microprocessor 514 to ensure that line removal and duplication in the modified video signal does not destroy the normal phase sequence of the color subcarrier reference bursts contained in the video line. It will be done.

If the output of flip-flop 522 indicates that the next field is to be shortened by, for example, two lines, microprocessor 514 reduces the field by an amount equal to two video signal lines as the next address of latch 515. The first offset stored in latch 511 is used to determine the vertical spacing starting address for the next vertical spacing, and the offset amount stored in latch 511 is
An amount of offset increased by an amount equal to one signal line is determined. If, on the contrary, the output of flip-flop 522 indicates that the paired fields are to be stretched by, say, two lines, then the microprocessor selects the next address as the next address to latch 515. determines the vertical spacing start address of the field of latch 510 and as the next offset amount of latch 510.
The offset amount stored in 11 is reduced by an amount equal to two video signal lines.

When the current read address reaches the vertical interval start address in latch 515, comparator 518 establishes consistency and flip-flop 513 is clocked to output signal N/=0, now provided by microprocessor 514.
Accordingly, the signal SEM is changed to 0, and an interrupt to the microprocessor 514 (block 600,
Figure 6) occurs. This new select=0 causes selector 509 to select an offset from latch 511 to continue reading from memory;
Since the offset amount is equal to the offset amount in , reading continues sequentially.

In response to this interrupt, the microprocessor 5
14 reads the signal select (block 60
1) determine its new state (block 60).
2). In this case, signal select=0, and in response, microprocessor 514 selects signal N/
V is set to 1 (opposite of signal select) (block 603), and this new value of signal N/, the determined offset amount for latch 510, and the determined address for latch 515 are then applied to this latch. and outputs it (block 604).
The microprocessor 514 then locks the latch 52.
The starting address of another vertical interval from 0 is read (block 605) and the output of signal O/E and flip-flop 522 is read. From this information, microprocessor 514 determines the next offset amount for latch 511 and the next address for latch 515 as previously described (block 606). For example, if the next field has a normal length of 262.5 lines, microprocessor 514 will select latch 515.
Using the associated vertically spaced starting address for and the same amount of offset in latch 510 for latch 511. The microprocessor 514 then waits for the next interrupt (block 6).
07), in response the above sequence is repeated for block 602. Since signal SELECT is 1 at this time, block 608 is reached in which signal N/ is set to 0, and then in block 609 this signal N/ and the offset amount determined for latch 511 and the address for latch 515 are determined. is output to these latches, which causes block 605
leading to. The above sequence is repeated as previously described.

From the above description, it can be seen that in the case of a field to be shortened by, for example, two lines, comparator 518 establishes consistency and an interrupt occurs two lines before the start of the next vertical interval, and selector 518
It will be seen that as a result of the switch of 9, the offset suddenly changes by two lines, so that reading continues for this next vertical interval.

Thus, the last two lines of this field are not read from memory. On the contrary, for example 2
For a field that extends to a line, the comparator establishes consistency, an interrupt occurs at the beginning of the next vertical interval, and as a result of the select 509 toggle, the offset suddenly changes by two lines, so the readout The last two lines of the field are read out from memory again before continuing by a vertical interval. Thus, the field length of the modified video signal is changed by subtracting lines from the end of each field or by adding duplicate lines to the end of each field. It is. As already mentioned, such changes in field length are not noticeable in normal playback and viewing of video signals on conventional television receivers, if done slowly as described above, but they do and video tape, which depends on its operation on a video signal with a frame length.
This prevents the recorder from properly recording the video signal.

As mentioned above, since the modified video signal has variable field and frame lengths,
It cannot be recorded properly on a video tape recorder. Unlike prior art configurations in which reconfiguration of the normal vertical spacing is easily possible at low cost and thus impairs the encoding operation by allowing recording of the video signal, the modified video signal of the present invention is It cannot be easily and economically converted into a suitable form. In fact, the decoder for converting the modified video signal into a suitable form for recording must be substantially as complex as the encoders described above with respect to FIGS. 1-6. While the cost of a single encoder can be justified for television transmission systems as mentioned above, the comparable cost of a decoder for individual use in a video tape recorder is generally prohibitive. it is conceivable that.

Although particular embodiments of the invention have been described in detail, many modifications and applications are possible without departing from the scope of the invention as defined in the claims.

As explained above, according to the video signal modification method of the present invention, from a video signal such as an NTSC video signal in which a field of a fixed length consisting of a desired number of video lines is continuously repeated,
Although a television receiver can properly reproduce images, a video signal recorder such as a VTR can produce a modified video signal that cannot be properly recorded.

[Brief explanation of the drawing]

1 is a block diagram illustrating a TV transmission system including a video signal encoder operative in accordance with the present invention to produce a modified video signal; FIG. 2 is a block diagram of a TV transmission system including a timing extraction device, a memory device, and control circuitry; Block diagram showing a signal encoder,
FIG. 3 is a block diagram showing the timing extraction device.
FIG. 4 is a block diagram of the memory on the same sheet as FIG. 1, FIG. 5 is a block diagram of the control circuit, and FIG. 6 is a flowchart showing the operation of the control circuit. 10...Program source 11...Video signal encoder, 12...Transmission system, 13...
...Cable, 14...Channel converter,
15... Television receiver, 200... Filter, 201... Timing extraction device, 202...
A/D converter and latch, 203...memory,
204...Control circuit, 207...Digital/analog converter and latch, 208...Filter and equalizer, 300...Color burst extractor, 301...Color burst phase locked loop, 302...PLL and frequency divider 304...Line counter, 305...Field counter, 400...ECL/TTL converter and RAM,
401,404...shift register, 402,4
03...Ratsui, 500,504...Address/
Selector, 501... Counter, 502...
PROM, 503... Latch, 505, 506...
... Bus, 507 ... Period counter, 508 ... Adder, 509 ... Selector, 510, 511, 5
12,515,520...Latch, 513...Flip-flop, 514...Microprocessor, 516...Common bus, 517...Line, 51
8...Comparator, 519...AND gate,
521...Noise source, 522...Flip-flop.

Claims (1)

[Claims] 1 When video lines of a video signal in which a field of a fixed length consisting of a desired number of video lines is continuously repeated are sequentially written into a memory, and when the video lines written to the memory are sequentially read out, one field is The field length can be changed by selectively changing the number of video lines included in one field by not reading out the video lines at the end of the period, or by adding extra video lines at the end of one field period. A method of modifying a video signal, the method comprising: producing a modified video signal of variable intensity.