JPH0470953A - Parallel processing processor - Google Patents

Abstract

PURPOSE:To transmit the information at a high speed among plural processors by comparing the reception processor No. of a packet signal with a proper processor No. in order to fetch the packet signal to an operation processing part or to transfer the packet signal to another processor. CONSTITUTION:A data reception processor No. A added to each head part of packet signals P1 and P2 is compared with a processor No. set previously to the processor. When the coincidence is secured between both Nos, the signals P1 and P2 are fetched by an arithmetic part 32 of a parallel processing processor 20 and a prescribed normal processing operation is carried out. If no coincidence is obtained between both Nos, both signals P1 and P2 are never fetched by the part 32 and transferred to another processor as they are from the I/O ports 26 and 28 via an input/output buffer 46. As a result, the memory access time is shortened and the information is transmitted at a high speed among plural processors.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a parallel processing processor suitable for sequentially transferring information signals between a plurality of processors in a packet communication system or the like.

- In layer details, the receiving processor number in the information formed at the beginning of the packet signal is compared with the unique processor number set in advance for the processor, and if they match, the packet is The packet is taken into the arithmetic processing unit of the processor, and if there is a mismatch, the packet is transferred to another processor, thereby speeding up the transmission of information between the plurality of processors.

[Prior Art] FIG. 4 shows a plurality of processors that are conventionally employed in packet communications and are installed in devices that perform parallel processing.

This example is a processor 2 with internal or external memory.
．． 4.6.8 are connected via communication lines 14, 16°l8.

Packet signals are sequentially transferred between the processors 2, 4, and 6.8 by storing and transmitting known information (message signals).

Furthermore, when information is transmitted between processors that are not directly connected, for example, from processor 2 to processor 6,
When transmitting information, first, the processor 2 to which the information has been supplied creates a packet signal having the number of data words as a header, and transmits the packet signal to the processor 4 via the communication line 14.

After the processor 4 detects that a packet has been input by an interrupt signal or the like, it writes data for the number of data words into a predetermined area of the memory in a packet input process. Subsequently, the processor 4 interprets the information attached to the packet read from the memory area, identifies that the destination of this packet is the processor 6, and transmits the packet read again from the memory via the communication line 16. processor 6
Transfer to. After the processor 6 detects that a packet has been input by an interrupt signal or the like, it writes data for the number of data words into the memory in a packet input process, and arithmetic processing is performed.

[Problem to be Solved by the Invention] However, in the parallel processing processor according to the above-mentioned conventional technology, for example, in the above-mentioned processor 4, which is not directly connected by a communication line, information is temporarily written in a predetermined area of the memory. Thereafter, the stored information is read out, the packet information is interpreted, the packet signal is identified as being transmitted to the processor 6, and is transmitted to the processor 6 via the communication line 16. Compared to directly connected processors, processors that are not directly connected in this way require more processing time due to a series of memory accesses due to packet signal input/output, which reduces processing power and results in lower processing power. However, it has the drawback that the information transmission speed is delayed.

The present invention has been made in view of the above points, and an object thereof is to provide an excellent parallel processing processor that can transmit information between a plurality of processors at high speed.

[Means for Solving the Problems] In order to solve the above problems, the parallel processing processor of the present invention has a plurality of processors connected through a communication line, and a receiving processor number and the number of information words are formed at the beginning. A parallel processing processor that sequentially transfers packet signals, which includes a storage means that stores and holds a unique processor number set in the processor, and a memory means that compares the received processor number and the processor number and outputs a judgment signal of match or mismatch. and a packet selection means that is supplied with a match determination signal and takes the input packet signal into an arithmetic processing unit, or is supplied with a mismatch determination signal and transfers the packet signal to another processor. It is characterized by

[Operation] In the parallel processing processor of the present invention configured as described above, the receiving processor number in the information formed at the head of the packet signal is compared with the unique processor number preset for the processor, If they match, the packet is taken into the processor's internal arithmetic processing unit, and if they do not match, the packet is transferred to another processor. At this time, memory access time such as storage of information and reading is reduced, resulting in faster transmission of information between multiple processors.

[Example] Next, an example of the parallel processing processor according to the present invention will be described in detail below with reference to the accompanying drawings.

FIG. 1 is a block diagram showing the configuration, FIG. 2 is a block diagram showing the packet selector in detail, and FIG. 3 is a diagram showing the packet configuration.

First, the configuration will be explained. In FIG. 1, 20 is a parallel processing processor according to the present invention, and this parallel processing processor 20 has two communication lines 22a, 22b, 24a, 24a, 22a, 22b, 24a, 22b, 24a, 22a, 22b, 24a, 22a, 22b, 24a, 22a, 22a, 24a, 24a, 24a, 24a, 22a, 24a, 24a, 22a, 24 , 24 , 24 , 24 , 24 , 24 , 24 , 24 , 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, and have e?
24b is connected. A packet signal P1 is input to this communication port $22a, transferred by the parallel processor 20, and sent out from the communication line 24a. Conversely, the packet signal P2 is input from the communication line 24b, transferred by the parallel processing processor 20, and sent out from the communication line 22b.

Here, the parallel processing processor 20 has communication lines 22a, 2
an input/output (Ilo) port 26 to which 2b is connected;
I10 boat 28 to which communication lines 24a and 24b are connected
is provided, and further includes a packet selector 30 to which the I10 port) 26 and 28 are connected, and this packet selector 3
an arithmetic unit 32 that takes in the packet signal P1 or the packet signal P2 outputted from 0 and performs predetermined processing;
Packet signal P output from 10 boats 26.28,
Alternatively, a packet determining unit 34 is provided which is supplied with the packet signal P2 and sends a determination signal S to the packet selector 30 as to whether this signal should be transferred as is or taken in. Furthermore, it is provided with a register 36 that stores and holds a unique processor number of this parallel processing processor 20.

FIG. 3 shows the packet selector 30 in detail.

This packet selector 30 has a human output buffer 42 connected to the 110 port 26, a human output buffer 44 connected to the 110 port 28, and an I10 port 26 and an I10 port 26.
It has a human output buffer 46 provided between the boats 28. The output buffers 42, 44, 46 are amplifiers 42a, 42b, respectively, as can be easily seen from the figure.

44a, 44b, 46a, and 46b, and further supplied with the determination signal S from the packet determination unit 34 and the input port identification signal S2, the output buffers 42, 44.4
6 and a buffer switching circuit 50 that sends out a switching signal for instructing the reception or passage of the packet signal Pl v Pt.

Further, FIG. 3 shows the configuration of packet signals P+ and Pt. The packet signals P, , P2 have the data receiving processor number A, the number of data words B, and the data C sequentially formed at the leading end.

Next, the operation in the above configuration will be explained.

When a packet signal P is input to the 110 port 26, the reception processor number A formed at the beginning of the packet signal P1 shown in FIG.
is input. The packet determination unit 34 compares the received processor number A with the unique processor number of the parallel processing processor 20 preset in the read register 36, and outputs a determination signal S1 of match or mismatch to the packet selector 30. At the same time, it outputs to the packet selector 30 an input port identification signal S indicating that the packet signal P has been input from the I10 port 26. This determination signal S1 and input port identification signal St are held until the transfer of one packet signal P1 is completed. Then, in the packet selector 30, the determination signal S1 and the input port identification signal S2 are input to the buffer switching circuit 50.

Here, if the judgment signal S1 is the above match, the buffer control signal S7 is turned ON, and at the same time the buffer control signal Ss
, Ss is turned OFF, the human output buffer 42
The amplifier 42a is operated. That is, the respective amplifiers 44a, 4 of the output buffers 44, 46 are opened.
6b is inactive, ie, closed. As a result, I1
The packet signal P input from the 0 port 26 is supplied to the arithmetic unit 32 via the input/output buffer 42. Furthermore, if the determination signal S1 does not match as described above, the packet selector 30 outputs the buffer control signal S7. By turning S* off and turning on the buffer control signal S, the amplifier 46a of the human output buffer 46 is operated. That is, the amplifier 42a of the output buffer 42.44,
44a is inactive, ie, closed.

As a result, the packet signal P1 input from the I10 port 26 is transmitted to the I10 port 28 via the human output buffer 46.
will be output as is.

Here, the case where the packet signal P2 is input from the I10 boat 28 will be explained. In this case, the operation is opposite to that of the packet signal P described above. That is, the packet signal P2
The reception processor number A at the beginning of is the packet determination unit 3.
4 is input. The packet determination unit 34 compares the input reception processor number A with the unique processor number of the parallel processing processor 20 preset in the register 36, and outputs a determination signal S of match or mismatch to the packet selector 30. .

At the same time, it outputs to the packet selector 30 an input port identification signal S indicating that the packet signal P2 has been input from the I10 boat 28.

This determination signal SI and input boat identification signal S2 are held until the transfer of one packet signal P2 is completed.

In the packet selector 30, the determination signal S input boat identification signal S2 is input to the buffer switching circuit 50. Here, if the determination signal S1 is the above match, the buffer control signal S is turned ON, and at the same time, the buffer control signal S7. S
By turning s off, the amplifier 44b of the human output buffer 44 is operated, ie, opened, and at the same time, the respective amplifiers 42a and 46b of the human output buffer 44, 46 are not operated, ie, closed. As a result, the packet signal P2 input from the I10 port 28 is supplied to the arithmetic unit 32 via the human output buffer 44. Furthermore, if the determination signal S1 does not match as described above, the packet selector 30 outputs the buffer control signal S7. By turning off the signal S and turning on the buffer control signal S, the human output buffer 46
The amplifier 46b of the output buffer 42.44 is activated, ie, opened, and the amplifiers 42b and 44b of the human output buffer 42.44 are inactivated, ie, closed. This allows I10 port 28
The packet signal P input from the input/output buffer 46
The signal is output as is from the I10 port 26 via the I10 port 26.

In this way, the reception processor number A of the data attached to the beginning of the packet signal P, ,P is compared with the unique processor number preset for the processor, and if the judgment is that they match Then, the packet signals P, , P, are taken into the arithmetic unit 32 inside the parallel processing processor 20 and subjected to normal predetermined processing. If the determination is that they do not match, the packet signals PI and P2 are not taken into the arithmetic unit 32 and are transferred as they are from the I10 boat 26.28 to another processor via the human output buffer 46. At this time, memory access time such as storage and reading of information is reduced, resulting in faster transmission of information between multiple processors.

In the above embodiment, there are two communication lines connected to the parallel processing processor, but three or more communication lines, that is, three or more packet signals, are judged and switched in the same manner as above, and the same operation is performed. Effects can also be obtained.

Furthermore, two communication lines 22a, 22b, 24a, 24
b consists of two communication paths with different data transfer directions, but it uses only one communication path to transfer data in both directions, a so-called time division (TDM) method, which is similar to the above. Obtaining effects is also included in the present invention.

[Effects of the Invention] As understood from the above description, according to the parallel processing processor of the present invention, the reception processor number in the information formed at the head of the packet signal and the unique processor preset in the processor The numbers are compared, and if they match, the packet is taken into the processor's internal arithmetic processing unit, and if they don't match, the packet is transferred to another processor, making it easy to read out and accumulate information. This has the advantage of reducing memory access time such as, and as a result, speeding up information transmission between multiple processors.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the parallel processing processor of the present invention, FIG. 2 is a block diagram showing details of the packet selector shown in FIG. 1, and FIG. 3 is a block diagram showing the configuration of an embodiment of the parallel processing processor of the present invention. FIG. 4 is a diagram showing the structure of the packet signal employed. FIG. 4 is a connection diagram of a parallel processing processor according to the prior art. 22a, 22b, 24a, 24b---communication line 26.
28... I10 boat, 30... Packet selector, 32... Arithmetic unit, 34... Packet determination unit, 3
6...Register, 42.44.46...Person output buffer, 42a, 42
b, 44a, 44b, 46a, 46b... amplifier,
P+, Pt...packet signal, Sl...judgment signal,
S,...Input port identification signal, Sv, S*, S*...
・Buffer control signal. Patent applicant Brother Industries, Ltd.

Claims (1)

[Claims] (1) A parallel processing processor in which multiple processors are connected via a communication line and transfers a packet signal in which a receiving processor number and the number of information words are formed at the beginning, and a unique processor number set for each processor. a storage means for storing and holding the received processor number; a determining means for comparing the received processor number and the processor number and outputting a determination signal of a match or mismatch; 1. A parallel processing processor comprising: a packet selection unit that transfers a packet signal to another processor by inputting the packet signal into an arithmetic processing unit or by being supplied with a non-coincidence determination signal.