JPH0472269B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an information processing device, and particularly to a logic simulation method using history registration suitable for shortening computer processing time.

[Background of the invention]

As the scale of information processing apparatuses increases, the amount of computer processing time required for logic simulations also increases, and there is a demand for improvements in the processing speed of logic simulations.

FIG. 1 shows an example of an input/output configuration based on a conventional logic simulation method. In the figure, 1 is a gate logic file (GLF) that describes the signal connection state of the logic circuit to be simulated;
2 is a simulation data file (SDF) in which simulation input/output conditions, etc. are described.
A logic simulation is executed using the information written in the gate logic file 1 and the simulation data file 2 as input, and the results are outputted to the list 3.

FIG. 2 shows a logic simulation method using the above conventional input/output configuration. As shown in FIG. 2a, an AND gate 4 to which two signals A and B are input and a signal C is output will be explained as an example. Here, consider that signal A corresponds to 2 ¹ and signal B corresponds to 2 ⁰ . As shown in Figure 2b, the input signals A and B are "00", "01",
If it changes to “11”, “01”, “00”, “10”, “11”,
Corresponding to this input, the output C is “0”, “0”,
It changes as "1", "0", "0", "0", "1".
In this case, in the conventional logical simulation method,
The value of output C is calculated every time the values of inputs A and B change. For example, if inputs A and B in the fourth cycle are "01", inputs A and B in the second cycle are "01". ”, the logic simulation is performed again and the value of the output C is calculated. Similarly, the value of the output C is calculated for the input "00" in the fifth cycle, regardless of the input "00" in the first cycle, which is the same input.

As mentioned above, in conventional logic simulation methods, output values are calculated each time in response to changes in input. Especially in the case of large-scale logic circuits,
The disadvantage is that the calculation processing time for logical simulation is long.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned points, and an object of the present invention is to provide a logical simulation method using history registration that is effective in shortening the computer processing time of an information processing device.

[Summary of the invention]

The main point of the present invention is that, in order to shorten computer processing time for logic simulation, a logic circuit is divided into arbitrary logic blocks, and the input values and output values of the logic blocks are registered as a history. When a value occurs, by immediately reading out the registered output value and giving an output signal,
This eliminates the calculation of output values based on input values and reduces computer processing time.

[Embodiments of the invention]

An embodiment of the present invention will be described below based on the drawings.

FIG. 3 is a diagram showing the input/output configuration of the logic simulation method according to the present invention. In this figure, parts with the same reference numerals as those in FIG. 1 indicate the same or corresponding parts (hereinafter, the same applies to other drawings). 5 summarizes logical functions in appropriate units,
Each is a functional logic file (FLF) whose function is described using Boolean expressions, truth tables, etc. 6 is structurally the same as the gate logic file (GLF) 1 in FIG. This is a gate logic file (GLF) automatically generated by a conversion program using the logic file 5 as input.

A logic simulation is executed using the information written in the function logic file 5 and the gate logic file 6 as input, and the results are output to list 3.

FIG. 4 is a diagram showing a logic simulation method according to the present invention, and assumes that inputs A, B, output C, and the values of these inputs and outputs, as well as AND gate 4, are the same as those described in FIG. 2 above. . In the same figure, first, when looking at the valid flag FFO for the value "00" of inputs A and B in the first cycle, it is "0".
It can be seen that this input/output value is not registered in the history table. Therefore, the value of output C for the value "00" of inputs A and B is calculated by logic simulation, the input/output value is registered in the history table, and the corresponding valid flag EFO is set to "1". The value of inputs A and B in the 2nd and 3rd cycles is “01”,
Valid flag EF1 also corresponds to “11” input,
Since both EF3 are "0", calculate the value of output C in the same way as in the first cycle, register the input/output values at that time in the history table, and set the corresponding valid flags EF1,
Set EF3 to “1”.

Next, for the value "01" of inputs A and B in the fourth cycle, this case has already occurred in the second cycle, and the valid flag EF1 is "1", so in this case, The output value is read from the history table and given to output C. Then, calculation of the output value based on the values of inputs A and B is not performed. The same process is performed from the 5th cycle onwards.

As described above, in the logic simulation method according to the present invention, when the input value occurs for the first time, the output value is calculated from the input value, is given to the output signal, and the input/output value is registered in the history table, and the corresponding response is taken. Set the valid flag (EF*, *: 0 to n) to “1”
Set to . Also, if the input value has already occurred,
If it is registered in the history table (EF*="1"),
Referring to the history table, the corresponding output value is read and applied to the output signal, and the value of output C based on inputs A and B is not calculated. The same procedure is performed after the 5th cycle.

Next, the access operation of the history table will be explained.

FIG. 5 is a block diagram showing a logic circuit model for explaining the history table access operation, in which a plurality of inputs IN1 to IN8 are input to the logic circuit model 7, and a plurality of outputs OUT1 to OUT3 are output. Ru.

7 to 9 are diagrams for explaining the specific operation of the history table in the logic circuit model 7,
The input table 8 and the history table 9 are generated corresponding to the functional description unit of the functional logic file (FLF) 5. Input table 8 contains input values, valid flag (EFn),
If the valid flag is "1", the registered content in the history table 9 is specified, but a pointer address is set. History table 9 shows the input values and output values, the delay time from input to output corresponding to each output signal, the valid bit (EN bit) corresponding to the input value,
Reference bits (RF bits) for determining priorities are also set.

In history table 9, it is not efficient to register input and output values for all cases of input values in terms of computer memory capacity and computer processing time. The so-called LRU method (Least Recently Used
(rule) to determine the priority order and register only the top ones. Therefore, if necessary, the registered contents may be replaced.

FIG. 6 is a diagram illustrating a priority determination method using the LRU method. As shown in FIG. It is expressed by the truth table shown in ~f. In FIG. 6, "〓" indicates the initial value, "P" indicates the priority, and "" indicates the accessed node number.

Now, when a node is accessed, the bit in the row direction is set to "1" and the bit in the column direction is set to "0", and each node
Consider the case where accesses are made in the order of 2, 3, 4, and 1. If node 1 is accessed first, node 1
The bit in the row direction is set to “1”, the bit in the column direction is set to “0”, and the truth table is set to the sixth
It will look like Figure b. In this case, the priority P of node 1 is 1 and the priority P of other nodes 2, 3, and 4 is 2. Subsequently, when nodes 2, 3, and 4 are sequentially accessed, the truth table changes as shown in FIG. 6c, d, and e. When node 1 is accessed in this state, the bit in the row direction of node 1 is set to "1" and the bit in the column direction is set to "0", as shown in FIG. As a result, the priority P of node 2 becomes 4, which means that it has not been accessed for the longest period of time among the four nodes. From this, when priorities are ranked in order of recentness of access time, node 2 with all bits set to "0" has the lowest priority when looking at the truth table in the row direction.

The access operation of the history table 9 using the above LRU method will be explained below.

FIG. 7 shows the initial registration operation in the history table 9. “01” 16 is input to the logic circuit model 7 shown in FIG.
However, assume that bit 2 is output after 6nS.

First, since this is initial registration, the valid flag (EF1) of input table 8 corresponding to input value “01”16 is “0”.
Therefore, the input value for this case is not registered in the history table 9 (see FIG. 7, 2).

Therefore, based on this input value, we simulate the logic circuit, calculate the output value, give that value to the output signal, and write the input/output value in the valid bit (EN bit) "0" column of history table 9. register.
Along with registration, the EN bit is set to "1", the reference bits (RF bits) 1 to 4 of the row concerned are set to "1", and the four RF bits of the column corresponding to the row number are set to "0".
Then, the input value is set to "01" 16, the output value is set to "101", and the delay time from input to output is set corresponding to each output bit (see FIGS. 7, 2 and 3).

After registration, read the input value “01” and set the valid flag (EF1) of the corresponding input table to “1”.
The start address value of the registration field in the history table 9 is set as a pointer. Below, the output is “100” for the input value “5A” 16, and “001” for the input value “FF” 16.
The output of "010" is registered sequentially for the input value "00" using the same method.

FIG. 8 shows the operation of referring to the history table 9 registered as described above. The input value “FF” 16 is input to the logic circuit model 7, and the output value is “011”.
Bit 0 and bit 2 become bit 1 after 6 ns after 5 ns.
Assume that the following is output.

Since the valid flag (EF225) of the input table 8 corresponding to the input value "FF" 16 is "1", it can be seen that the input/output value of this case is registered in the history table 9 (see Fig. 8, 1). ).

Therefore, by using the pointer of input table 8, history table 9
, read the corresponding output value “011”, and
Bit 0 and bit 2 after 5ns, bit 6 after 6ns
After a predetermined period of time has elapsed, the output value is given to the output signal. Thereafter, the reference bit (RF bit) in the history table 9 is updated in the same manner as in the case of initial registration (see FIGS. 8, 2 and 3).

FIG. 9 shows an operation for updating the registered contents of the history table 9. Assume that the input value "FE" 16 is input to the logic circuit model 7, the output value is "001", bits 0 and 2 are output after 5 ns, and bit 1 is output after 6 ns.

Since the valid flag (EF254) of the input table 8 corresponding to the input value "FE" 16 is "0", it can be seen that the input/output value in this case is not registered in the history table 9 (see Fig. 9, 1). ).

Therefore, the logic circuit 7 is simulated based on the input value "FE" 16, the output value is calculated, and the value is given to the output signal. Next, check the valid bits (EN bits) in history table 9, and since all EN bits are "1", there are no empty registration fields, so
Search for the registered content with the lowest priority. In this case, the registered content corresponding to the input value "01" at the top of the history table 9 is considered to have the lowest priority because all reference bits (RF1 to RF4) are "0" (see Fig. 9, 2). , 3).

The lowest priority input value "01" of the history table 9 is read out, and the corresponding valid flag (EF1) of the input/output table 8 is reset to "0" (see FIG. 9).

After that, the input/output value of the output value "001" corresponding to the input value "FE" 16 is registered in the lowest priority registration row of the history table 9 in the same manner as the initial registration, and the related reference bit is (RF bit) is updated.

Finally, read the new input value “FE”16,
The valid flag of input/output table 8 corresponding to this (FE25
4) is set to "1" and the start address value of the registration column of the history table 9 is set as a pointer.

As explained above, in the above embodiment, the input table 8 and the history table 9 are created for each function description unit of the functional logic file (FLF) 5, and the simulation results are registered in association with the input values. , when the same input value occurs, without calculating the output value by logic simulation, the history table 9
By reading the output value from and applying it to the output signal, the calculation processing time of logic simulation is shortened.

〔Effect of the invention〕

As explained above, in the present invention, when the same input value is applied to the same logic block, the output value is immediately read from the registration means and applied to the output signal. An output value can be given to an output signal without calculating an output value, which has an excellent effect on speeding up logic simulation.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the input/output configuration of a conventional logic simulation, FIG. 2 is a logic circuit example and timing chart for explaining the conventional logic simulation method, and FIG. 3 is an input/output configuration of a logic simulation according to the present invention. 4 is a block diagram showing the output configuration, FIG. 4 is a logic circuit example and timing chart for explaining the logic simulation method according to the present invention, FIG. 5 is a diagram showing a logic circuit model for explaining the present invention, and FIG. 6 is a block diagram showing the output configuration. The figure shows a method for determining priorities using the LRU method, Figure 7 is a diagram for explaining the initial registration operation to the history table in the present invention, and Figure 8 shows the reference operation from the history table in the present invention. FIG. 9 is a diagram for explaining the updating operation of the registered contents of the history table in the present invention. 1...Gate logic file, 2...Simulation data file, 3...List, 4...
AND gate, 5...Functional logic file, 6...
Gate logic file, 7...Logic model, 8...
Input table, 9...history table.

Claims (1)

[Scope of Claims] 1. A logic simulation device that divides a logic circuit into logic blocks of logic function units and uses an output value determined for each logic block corresponding to an input value as an output signal, wherein the input value and It has a registration means that can register the output value as a pair, and when an input value that is not registered in the registration means is generated, an output value corresponding to the input value is determined and given as an output signal, and the When an input value registered in the registration means is generated, the output value registered in the registration means is read out and given as an output signal, and an input value not registered in the registration means is generated. , and when there is no vacancy in the registration means,
A logic simulation device characterized by deleting a set with the lowest priority from among already registered sets and registering a newly determined set.