JPH0472651U - - Google Patents
Info
- Publication number
- JPH0472651U JPH0472651U JP1990116188U JP11618890U JPH0472651U JP H0472651 U JPH0472651 U JP H0472651U JP 1990116188 U JP1990116188 U JP 1990116188U JP 11618890 U JP11618890 U JP 11618890U JP H0472651 U JPH0472651 U JP H0472651U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- view
- chip
- circuit board
- wiring pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/547—Dispositions of multiple bond wires
- H10W72/5475—Dispositions of multiple bond wires multiple bond wires connected to common bond pads at both ends of the wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/921—Structures or relative sizes of bond pads
- H10W72/926—Multiple bond pads having different sizes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/931—Shapes of bond pads
- H10W72/932—Plan-view shape, i.e. in top view
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Wire Bonding (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Description
第１図は本考案の第１実施例を示す半導体装置
の平面図、第２図はその正面図、第３図は本考案
の第２実施例を示す半導体装置の平面図、第４図
はその正面図、第５図は本考案の第３実施例を示
す半導体装置の平面図、第６図はその正面図、第
７図は本考案の第４実施例を示す半導体装置の平
面図、第８図は本考案の第５実施例を示す半導体
装置の平面図、第９図は従来の半導体装置の平面
図、第１０図はその正面図である。
１１……回路基板、１２……配線パターン、１
３……ＩＣチツプ、１４……パツド、１５……ボ
ンデイングワイヤ。
1 is a plan view of a semiconductor device showing a first embodiment of the present invention, FIG. 2 is a front view thereof, FIG. 3 is a plan view of a semiconductor device showing a second embodiment of the present invention, and FIG. 4 is a plan view of a semiconductor device showing a second embodiment of the present invention. 5 is a plan view of a semiconductor device showing a third embodiment of the present invention, FIG. 6 is a front view thereof, and FIG. 7 is a plan view of a semiconductor device showing a fourth embodiment of the present invention, FIG. 8 is a plan view of a semiconductor device showing a fifth embodiment of the present invention, FIG. 9 is a plan view of a conventional semiconductor device, and FIG. 10 is a front view thereof. 11... Circuit board, 12... Wiring pattern, 1
3...IC chip, 14...pad, 15...bonding wire.
Claims (1)
成された配線パターンに応じて変更したことを特
徴とする半導体装置。 A semiconductor device characterized in that the pad position of an IC chip is changed according to a wiring pattern formed on an integrated circuit board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990116188U JPH0472651U (en) | 1990-11-07 | 1990-11-07 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990116188U JPH0472651U (en) | 1990-11-07 | 1990-11-07 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0472651U true JPH0472651U (en) | 1992-06-26 |
Family
ID=31864006
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1990116188U Pending JPH0472651U (en) | 1990-11-07 | 1990-11-07 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0472651U (en) |
-
1990
- 1990-11-07 JP JP1990116188U patent/JPH0472651U/ja active Pending