JPH0472732A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0472732A JPH0472732A JP18606090A JP18606090A JPH0472732A JP H0472732 A JPH0472732 A JP H0472732A JP 18606090 A JP18606090 A JP 18606090A JP 18606090 A JP18606090 A JP 18606090A JP H0472732 A JPH0472732 A JP H0472732A
- Authority
- JP
- Japan
- Prior art keywords
- film
- wiring
- semiconductor device
- layer
- furthermore
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 229910052802 copper Inorganic materials 0.000 claims abstract description 20
- 239000012535 impurity Substances 0.000 claims description 2
- 239000010410 layer Substances 0.000 abstract description 17
- 238000000034 method Methods 0.000 abstract description 7
- 230000000694 effects Effects 0.000 abstract description 4
- 239000000758 substrate Substances 0.000 abstract description 4
- 239000011229 interlayer Substances 0.000 abstract description 3
- 230000001681 protective effect Effects 0.000 abstract description 3
- 238000001312 dry etching Methods 0.000 abstract description 2
- 229910018594 Si-Cu Inorganic materials 0.000 abstract 1
- 229910008465 Si—Cu Inorganic materials 0.000 abstract 1
- 238000010438 heat treatment Methods 0.000 description 5
- 238000005245 sintering Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000009827 uniform distribution Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、半導体装置に関するものであり、特にAI
配線構造に係る。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device, and in particular to an AI
Related to wiring structure.
従来の半導体装置の一例を、ボンデイングパノド部分の
断面構造図で第2図に示す、この半導体装置は、Si基
板1上に眉間絶縁膜2としてNSG膜を成長させている
。またその上に、配線膜として、Stを1wt%含有す
るとともにCuを0.5wt%含有したAl−3i−C
u膜3を1μmの厚さに薫着している。さらに、表面保
護膜5として、プラズマSiN膜を成長させ、ボンデイ
ングパ・2ド部分をエツチング除去して、配wA膜であ
るAl−3i−Cu膜3の表面を露出させている。An example of a conventional semiconductor device is shown in FIG. 2 as a cross-sectional structural diagram of a bonding pane. In this semiconductor device, an NSG film is grown as a glabellar insulating film 2 on a Si substrate 1. Further, on top of that, as a wiring film, Al-3i-C containing 1 wt% of St and 0.5 wt% of Cu is formed.
The U film 3 is smoked to a thickness of 1 μm. Furthermore, a plasma SiN film is grown as a surface protection film 5, and the bonding pad 2 is etched away to expose the surface of the Al-3i-Cu film 3, which is the wafer A film.
従来の半導体装置の場合、Aj−3i−Cu膜3の蒸着
後のシンター処理により、SiやCuが表面側に移動す
るため、ワイヤボンドの接着性が劣化するという問題が
あった。In the case of a conventional semiconductor device, the sintering process after the deposition of the Aj-3i-Cu film 3 causes Si and Cu to move to the surface side, resulting in a problem in that the adhesion of wire bonds deteriorates.
つまり、従来例のようなAl−3i−Cu膜3単独のA
l配線膜である場合には、熱処理工程で、Si、Cuが
表面に移動すると、表面側の5ib
均一分布の場合の2倍の濃度になる場合もある。In other words, the A of the Al-3i-Cu film 3 alone as in the conventional example
In the case of a wiring film, when Si and Cu move to the surface during the heat treatment process, the concentration may become twice as high as that in the case of uniform distribution of 5ib on the surface side.
SiやCuを含んだAl配線膜は、一般に純粋なAl膜
4に比べて硬度が高いので、ワイヤボンド時のパワー条
件を厳しくしないと接着しな(なる。Since the Al wiring film containing Si or Cu generally has higher hardness than the pure Al film 4, it will not adhere unless the power conditions during wire bonding are strict.
パワーを上げると、チップへの衝撃が大きくなり、クラ
ンクを発生する可能性が出て(る、また、SiやCuの
濃度が高いAl膜はAuワイヤとの接着性が悪くなる。Increasing the power increases the impact on the chip, increasing the possibility of cranking (Also, the Al film with a high concentration of Si and Cu has poor adhesion to the Au wire.
この発明の半導体装置は、配線膜としてCu。 The semiconductor device of the present invention uses Cu as the wiring film.
Siの不純物を含む第1のAl膜上に、Cu、 S、
71度が第1のAn膜より低い(Cu、Siを全く含ま
ない場合もある)第2のAl膜を積層した2層構造のA
l配線膜を用いたものである。On the first Al film containing Si impurities, Cu, S,
A with a two-layer structure in which a second Al film is laminated with a temperature of 71 degrees lower than that of the first An film (which may not contain Cu or Si at all).
1 wiring film is used.
この発明の構成によれば、Cu、Si4度の異なる第1
および第2のAl膜を、Cu、Si1度の低い第2のA
n膜を上層にして、積層した2層構造をAJ配線膜とし
ているので、Al配線膜の蒸着後の熱処理工程で、Si
やCuがAl配線膜表面上に移動しても、Al配線膜の
表面のSiやCuの濃度が従来に比べて低い状態を維持
でき、ワイヤポンドの接着性への影響が小さくなる。According to the configuration of this invention, the first
And the second Al film is made of a second Al film with a low degree of Cu and Si.
Since the AJ wiring film has a two-layer structure with the n film as the upper layer, Si
Even if Si and Cu move onto the surface of the Al wiring film, the concentration of Si and Cu on the surface of the Al wiring film can be maintained lower than in the past, and the influence on the adhesion of the wire pond is reduced.
この発明の半導体装置の一実施例を、ポンディングパッ
ド部の断面構造図で第1図に示す。An embodiment of the semiconductor device of the present invention is shown in FIG. 1 as a cross-sectional structural diagram of a bonding pad portion.
この半導体装置は、Si基板1上に層間絶縁膜2として
、例えばLP−CVD法でNSC膜を約8000人の厚
さに成長させる。つぎに、Slを1wt%含有するとと
もにCuをQ、5wt%含有したAl5i−Cu膜3を
第1のAn膜として約8000人の厚さにスパッタ蒸着
する。さらにその上に、Si、 Cuを含まないAl膜
4を第2のAl膜として約2000人の厚さにスパッタ
蒸着する。In this semiconductor device, an NSC film is grown as an interlayer insulating film 2 on a Si substrate 1 to a thickness of approximately 8000 nm by, for example, the LP-CVD method. Next, an Al5i-Cu film 3 containing 1 wt % of Sl and 5 wt % of Cu is sputter-deposited as a first An film to a thickness of about 8,000 mm. Furthermore, an Al film 4 containing no Si or Cu is sputter-deposited as a second Al film to a thickness of approximately 2000 mm.
このようにしてAl/Al−3i −Cuの2層構造の
Al配線膜6にした後、Al配線膜6をドライウェット
法によりバターニングする。さらに、シンター処理とし
て、450℃、約30分の熱処理を行う。After forming the Al wiring film 6 having a two-layer structure of Al/Al-3i-Cu in this manner, the Al wiring film 6 is buttered by a dry wet method. Furthermore, heat treatment is performed at 450° C. for about 30 minutes as a sintering treatment.
つぎに、表面保護膜5として、例えばプラズマSiN膜
を約8000人の厚さに成長させ、380℃。Next, as the surface protection film 5, for example, a plasma SiN film is grown to a thickness of about 8,000 nm at 380°C.
約30分のシンター処理を行う。さらに、ポンディング
パッド部分のAl配線膜6のうち上層のAl膜4の表面
を露出させるため、ドライエツチングによりパターニン
グする。Perform sintering for about 30 minutes. Furthermore, in order to expose the surface of the upper Al film 4 of the Al wiring film 6 in the bonding pad portion, patterning is performed by dry etching.
この実施例の場合、AIl膜4の蒸着後と表面保護膜5
の成長後とにそれぞれ熱処理工程があり、これらの熱処
理工程で、AJ−3i −Cu膜3中のSi、Cuが表
面側、つまりkl−3i −Cu膜3の、1M膜膜中中
移動する。In the case of this embodiment, after the deposition of the Al film 4 and the surface protective film 5.
There is a heat treatment step after the growth of the AJ-3i-Cu film 3, and in these heat treatment steps, Si and Cu in the AJ-3i-Cu film 3 move to the surface side, that is, into the 1M film of the kl-3i-Cu film 3. .
ところが、この実施例のように、Al配線膜6を2層構
造とすることで、表面側でのSi、Cu濃度を0にして
おけば、熱処理で下層のAjl−5i−Cu膜3中のS
i、Cuが表面側に移動しても、上層のAI膜膜中中S
i、Cu11度は、それぞれ0.5wt%、0.2wt
%と、従来の場合よりも低い濃度を維持でき、ワイヤボ
ンディング性への影響は小さい状態になる。However, if the Al wiring film 6 has a two-layer structure as in this embodiment, and the Si and Cu concentrations on the surface side are set to 0, the heat treatment will reduce the concentration of Si and Cu in the lower layer Ajl-5i-Cu film 3. S
i, Even if Cu moves to the surface side, S in the upper layer of the AI film
i and Cu11 degrees are 0.5wt% and 0.2wt, respectively.
%, lower concentration than in the conventional case can be maintained, and the effect on wire bonding properties is small.
上記の実施例では、AI/Al−3i−Cuの2層構造
を示したが、これ以外に、SiをQ、5wt%含有する
とともにCuをQ、2@t%含有したAAl−3i−C
uを上層とし、Siを1wt%含有するとともにCuを
Q、5 w t%金含有たAn−3iCu膜を下層とす
るAl配線膜のように、上層の第2のAn膜のSi、C
ufi度が下層の第1のA!膜のSi、Cufi度より
低ければ、効果はある。In the above example, a two-layer structure of AI/Al-3i-Cu was shown.
Like an Al wiring film in which the upper layer is an An-3iCu film containing 1 wt% Si, Q Q, and 5 wt% gold, the Si, C of the second An film in the upper layer is
The first A with a lower ufi degree! It is effective as long as it is lower than the Si and Cufi degrees of the film.
この発明の半導体装置によれば、上層の第2のAl膜中
のSi、Cu濃度を下層の第1のAl膜中のSi、Cu
濃度よりも低(した2層構造のAl配線膜を用いている
ので、製造工程に熱処理工程が含まれていても、Al配
線膜の表面の5iCu濃度が下層の第1のAn膜よりも
高くはならず、ワイヤボンディング性への悪影響を防ぐ
ことができる。According to the semiconductor device of the present invention, the concentration of Si and Cu in the second Al film in the upper layer is lower than the concentration of Si and Cu in the first Al film in the lower layer.
Since we use a two-layered Al wiring film with a lower concentration than Therefore, an adverse effect on wire bonding properties can be prevented.
第1図はこの発明の一実施例の半導体装置のポンディン
グパッド部分の構造断面図、第2図は従来の半導体装置
のポンディングパッド部分の構造断面図である。
1・・・Si基板、2・・・層間絶縁膜、3・・・A7
膜−3i−Cu膜、4・・・Afll、5・・・表面保
護膜、6・・・Al配線膜
〔発明の効果〕FIG. 1 is a structural cross-sectional view of a bonding pad portion of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a structural cross-sectional view of a bonding pad portion of a conventional semiconductor device. DESCRIPTION OF SYMBOLS 1...Si substrate, 2...Interlayer insulating film, 3...A7
Film-3i-Cu film, 4... Afll, 5... Surface protective film, 6... Al wiring film [Effects of the invention]
Claims (1)
1のAl膜よりCu、Si濃度の低い第2のAl膜を積
層した2層構造のAl配線膜を用いたことを特徴とする
半導体装置。It is characterized by using an Al wiring film having a two-layer structure in which a second Al film having a lower Cu and Si concentration than the first Al film is laminated on a first Al film containing impurities of Cu and Si. semiconductor devices.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18606090A JPH0472732A (en) | 1990-07-13 | 1990-07-13 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18606090A JPH0472732A (en) | 1990-07-13 | 1990-07-13 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0472732A true JPH0472732A (en) | 1992-03-06 |
Family
ID=16181691
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18606090A Pending JPH0472732A (en) | 1990-07-13 | 1990-07-13 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0472732A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6366783B1 (en) | 1997-06-10 | 2002-04-02 | Nec Corporation | Radio paging receiver having time correction function |
-
1990
- 1990-07-13 JP JP18606090A patent/JPH0472732A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6366783B1 (en) | 1997-06-10 | 2002-04-02 | Nec Corporation | Radio paging receiver having time correction function |
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