JPH0547830A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH0547830A
JPH0547830A JP3207771A JP20777191A JPH0547830A JP H0547830 A JPH0547830 A JP H0547830A JP 3207771 A JP3207771 A JP 3207771A JP 20777191 A JP20777191 A JP 20777191A JP H0547830 A JPH0547830 A JP H0547830A
Authority
JP
Japan
Prior art keywords
film
etching
tin
mask
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP3207771A
Other languages
Japanese (ja)
Inventor
Kenichi Imai
健一 今井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP3207771A priority Critical patent/JPH0547830A/en
Publication of JPH0547830A publication Critical patent/JPH0547830A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/59—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/923—Bond pads having multiple stacked layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/934—Cross-sectional shape, i.e. in side view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Drying Of Semiconductors (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】 【目的】 TiN/Pt/Au 構造のボンディングパッドの形成
方法に関し, パッド形成時の熱処理によりパッド表面に
穴が発生するのを防止する方法を提供し, ボンディング
剥離の防止を目的とする。 【構成】 半導体基板１上にTiN 膜４, Pt膜５, Au膜６
を順に被着する工程と,該Au膜上の所定領域にAl膜７を
形成し，該Al膜をマスクにして, スパッタガスを用いた
逆スパッタ法により該Au膜及び該Pt膜をエッチングする
工程と，該Al膜をエッチング除去する工程と，該Au膜上
にレジスト膜８を形成し, 該レジスト膜をマスクにし
て，TiN 膜をエッチングする工程と, 該基板を熱処理す
る工程とを有するように構成する。 (57) [Summary] [Objective] Regarding a method of forming a bonding pad of TiN / Pt / Au structure, a method of preventing holes from being generated on the pad surface by heat treatment during pad formation is provided to prevent peeling of the bonding. To aim. [Structure] TiN film 4, Pt film 5, Au film 6 on semiconductor substrate 1.
And the step of depositing the Al film 7 in a predetermined region on the Au film, and the Au film and the Pt film are etched by a reverse sputtering method using a sputtering gas with the Al film as a mask. A step of etching and removing the Al film, a step of forming a resist film 8 on the Au film, etching the TiN film using the resist film as a mask, and a step of heat-treating the substrate. To configure.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は半導体装置の製造方法に
係り，特にハイブリッドIC等に用いられるTiN/Pt/Au 構
造のボンディングパッドの形成方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a bonding pad having a TiN / Pt / Au structure used for a hybrid IC or the like.

【０００２】ハイブリッドICは, チップのボンディング
にネイルヘッドボンディングが用いられる場合が多く,
その場合, ボンディングパッドはチップ上に絶縁膜を介
して順に積層されたTiN/Pt/Au構造を採用している。Hybrid ICs often use nail head bonding for chip bonding.
In that case, the bonding pad adopts a TiN / Pt / Au structure, which is sequentially laminated on the chip via an insulating film.

【０００３】[0003]

【従来の技術】従来のTiN/Pt/Au 構造のパッドをパター
ニングする際のPt/Au のエッチングは次のエッチャント
を用いたウエットエッチングにより行っていた。2. Description of the Related Art Etching of Pt / Au when patterning a pad having a conventional TiN / Pt / Au structure has been performed by wet etching using the following etchant.

【０００４】 Auに対するエッチャント： ヨウ素＋ヨウ化アンモン Ptに対するエッチャント： 王水Etchant for Au: Iodine + Ammonium iodide Pt: Etchant for aqua regia

【０００５】[0005]

【発明が解決しようとする課題】従来例のエッチングに
よりパターニングしたパッドは, その後約 450℃の熱処
理が加えられる。The pad patterned by the etching of the conventional example is then subjected to a heat treatment at about 450.degree.

【０００６】この熱処理により，パッド表面に穴が発生
し，この穴は寿命試験においてボンディング剥離の原因
となっていた。本発明は, パッド形成時の熱処理により
パッド表面に穴が発生するのを防止する方法を提供し,
ボンディング剥離の防止を目的とする。Due to this heat treatment, holes were formed on the pad surface, and these holes were the cause of peeling of the bonding in the life test. The present invention provides a method for preventing holes from being formed on the pad surface by heat treatment during pad formation,
The purpose is to prevent the peeling of the bonding.

【０００７】[0007]

【課題を解決するための手段】上記課題の解決は，半導
体基板(1) 上に窒化チタン(TiN) 膜(4）, 白金(Pt)膜
(5) , 金(Au)膜(6) を順に被着する工程と, 次いで, 該
Au膜(6) 上の所定領域にアルミニウム(Al)膜(7) を形成
し，該Al膜(7) をマスクにして, スパッタガスを用いた
逆スパッタ法により該Au膜(6) 及び該Pt膜(5) をエッチ
ングする工程と，次いで，該Al膜(7) をエッチング除去
する工程と，次いで, 該Au膜(6) 上にレジスト膜(8) を
形成し, 該レジスト膜(8) をマスクにして，該TiN 膜
(4）をエッチングする工程と, 次いで，該基板を熱処理
する工程とを有することを特徴とする半導体装置の製造
方法により達成される。[Means for Solving the Problems] To solve the above problems, a titanium nitride (TiN) film (4) and a platinum (Pt) film are formed on a semiconductor substrate (1).
(5), depositing the gold (Au) film (6) in sequence, and then,
An aluminum (Al) film (7) is formed in a predetermined area on the Au film (6), the Al film (7) is used as a mask, and the Au film (6) and the Au film (6) are formed by a reverse sputtering method using a sputtering gas. A step of etching the Pt film (5), then a step of etching away the Al film (7), and then a resist film (8) formed on the Au film (6). ) As a mask and the TiN film
This is achieved by a method for manufacturing a semiconductor device, which comprises a step of etching (4) and then a step of heat-treating the substrate.

【０００８】[0008]

【作用】本発明者は, パッド表面の穴の発生はPt/Au の
ウエットエッチングに問題があることに気付いて, 汚染
や反応物質からなる残渣を残さないように，ヨウ素や酸
等のエッチャントまたは反応ガスを使用しないでもエッ
チングできる方法として，スパッタガスとして清浄なAr
ガスだけを使用する逆スパッタ（スパッタエッチング）
によりエッチングできる次のような方法を開発した。[Function] The present inventor has noticed that the generation of holes on the pad surface has a problem in wet etching of Pt / Au, so that an etchant such as iodine or an acid or an acid or the like may be left so as not to leave a residue consisting of contamination or a reaction material. As a method that can be etched without using a reactive gas, clean Ar gas can be used as a sputter gas.
Reverse sputtering using only gas (sputter etching)
We have developed the following method for etching.

【０００９】本発明は，Arガスの逆スパッタによるAlの
エッチングレートはPt, Auに比べて約1/10 (Al：10Å/m
in , Pt, Au： 100Å/min) であるため，Alをマスクに
してPt, Auをエチングできることを利用した。According to the present invention, the etching rate of Al by reverse sputtering of Ar gas is about 1/10 that of Pt and Au (Al: 10Å / m).
in, Pt, Au: 100 Å / min), we used the fact that Pt and Au can be etched using Al as a mask.

【００１０】これによると, 従来のウエットエッチング
に比べ処理が簡単で, ２種類のエッチャントを使用しな
くてよくなった。また，使用する装置も他のドライエッ
チャを用いたとしても，反応ガスを使用しなくても良く
安全であり，装置内を汚染する心配がない。According to this, the process is simpler than the conventional wet etching, and it is not necessary to use two kinds of etchants. Further, even if another dry etcher is used as the device to be used, it does not need to use a reaction gas, and it is safe, and there is no fear of contaminating the inside of the device.

【００１１】[0011]

【実施例】図１ (A)〜(C) は本発明の実施例を説明する
断面図である。図において，半導体基板としてのシリコ
ン(Si)基板１上に形成されたAl配線２上に，層間絶縁膜
としてりん珪酸ガラス(PSG)膜３を成長し，Al配線２上
を開口する。1 (A) to 1 (C) are sectional views for explaining an embodiment of the present invention. In the figure, a phosphosilicate glass (PSG) film 3 is grown as an interlayer insulating film on an Al wiring 2 formed on a silicon (Si) substrate 1 serving as a semiconductor substrate, and an opening is formed on the Al wiring 2.

【００１２】次いで, スパッタ法により，基板上に厚さ
5000ÅのTiN 膜４, 厚さ1000ÅのPt膜５, 厚さ5000Åの
Au膜６を順に被着する。図１(B) において，スパッタ法
により，基板上に厚さ3000ÅのAl膜７を被着し，通常の
リソグラフィを用いてパターニングしてボンディングパ
ッド形成部にAl膜７を残す。Then, the thickness of the substrate is sputtered.
5000 Å TiN film 4, 1000 Å thick Pt film 5, 5000 Å thick
The Au film 6 is deposited in order. In FIG. 1 (B), an Al film 7 having a thickness of 3000 Å is deposited on the substrate by a sputtering method, and patterning is performed by using ordinary lithography to leave the Al film 7 on the bonding pad formation portion.

【００１３】次いで，残ったAl膜７をエッチングマスク
にして，逆スパッタによりAu膜６，Pt膜５をエッチング
する。 Au，Ptの逆スパッタ条件 スパッタガス： Ar ガス圧力 ： 3 mm Torr RF 電力 ： 1.5 KW バイアス電圧： 200 V 次いで，Al膜７をリン酸でエッチング除去する。Next, using the remaining Al film 7 as an etching mask, the Au film 6 and the Pt film 5 are etched by reverse sputtering. Reverse sputtering conditions for Au and Pt Sputter gas: Ar gas pressure: 3 mm Torr RF power: 1.5 KW Bias voltage: 200 V Then, the Al film 7 is removed by etching with phosphoric acid.

【００１４】図１(C) において，基板上にレジスト膜８
を被着し，パターニングしてボンディングパッド形成部
のAu膜６上のレジスト膜８を残す。次いで，ドライエッ
チングにより，パターニングされたレジスト膜８をマス
クにして，TiN 膜４をエッチングする。In FIG. 1C, a resist film 8 is formed on the substrate.
Is deposited and patterned to leave the resist film 8 on the Au film 6 in the bonding pad forming portion. Then, the TiN film 4 is etched by dry etching using the patterned resist film 8 as a mask.

【００１５】 TiN ドライエッチングの条件 反応ガス： SiCl4＋Cl2 ガス圧力： 0.01 Torr RF 電力： 400 W 次いで，基板を 450℃で熱処理する。Conditions for TiN dry etching Reaction gas: SiCl 4 + Cl 2 gas pressure: 0.01 Torr RF power: 400 W Then, the substrate is heat-treated at 450 ° C.

【００１６】図２は実施例を適用したデバイスの断面図
である。図において，１は基板，1Bは埋込層, 1Cはコレ
クタ, 1Bはベース, 1Eはエミッタ, 1CC はコレクタコン
タクト領域, ISOは素子分離領域, ２はAl配線, 3Aは層
間絶縁膜で二酸化シリコン(SiO2)膜, 3Bは層間絶縁膜で
PSG 膜, ４はTiN 膜，５はPt膜, ６はAu膜, ９はボンデ
ィングワイャである。FIG. 2 is a sectional view of a device to which the embodiment is applied. In the figure, 1 is a substrate, 1B is a buried layer, 1C is a collector, 1B is a base, 1E is an emitter, 1CC is a collector contact region, ISO is an element isolation region, 2 is Al wiring, 3A is an interlayer insulating film and is silicon dioxide. (SiO 2 ) film, 3B is an interlayer insulating film
PSG film, 4 is TiN film, 5 is Pt film, 6 is Au film, and 9 is bonding wire.

【００１７】次に工程の概略を説明する。 (1) バルク工程を完成する（バイポーラ素子を形成）。 (2) １層目Al膜を被着する。 (3）パターニングして１層目Al配線を形成する。 (4）PSG 膜を成長する。 (5) PSG 膜にボンディングパッド接続部を開口する。 (6) TiN/Pt/Au をスパッタする。 (7) Al膜をマスクにして, Arを用いた逆スパッタにより
Au＋Ptをエッチングする（本発明の要点）。 (8) Al膜を除去する。 (9) レジスト膜をマスクにして，TiN 膜をドライエッチ
ングする。 (10) 450℃の熱処理を行う。Next, the outline of the steps will be described. (1) Complete bulk process (form bipolar device). (2) Deposit the first Al film. (3) Patterning is performed to form the first layer Al wiring. (4) Grow the PSG film. (5) Open the bonding pad connection part in the PSG film. (6) Sputter TiN / Pt / Au. (7) Using Al film as a mask, reverse sputtering using Ar
Etching Au + Pt (gist of the present invention). (8) Remove the Al film. (9) Using the resist film as a mask, dry-etch the TiN film. (10) Heat treatment at 450 ° C.

【００１８】次に, 実施例の効果をみるために, 多数試
料について観察したところ，従来例では穴の発生する確
率は90％であったが，実施例では０％になった。Next, in order to see the effect of the embodiment, when a large number of samples were observed, the probability that holes were generated was 90% in the conventional example, but was 0% in the embodiment.

【００１９】[0019]

【発明の効果】本発明によれば, パッド形成時の熱処理
によってパッド表面に穴が発生するのを防止することが
できた。According to the present invention, it was possible to prevent the formation of holes on the pad surface due to the heat treatment at the time of pad formation.

【００２０】この結果, ボンディング剥離が防止され，
デバイスの製造歩留と信頼度が向上した。As a result, peeling of the bonding is prevented,
Improved device manufacturing yield and reliability.

【図面の簡単な説明】[Brief description of drawings]

【図１】 本発明の実施例を説明する断面図FIG. 1 is a sectional view illustrating an embodiment of the present invention.

【図２】 実施例を適用したデバイスの断面図FIG. 2 is a sectional view of a device to which the embodiment is applied.

【符号の説明】[Explanation of symbols]

１ 半導体基板でSi基板 ２ 配線， ３ 層間絶縁膜 ４ TiN 膜 ５ Pt膜 ６ Au膜 ７ 逆スパッタのマスクでAl膜 ８ レジスト膜 ９ ボンディングワイヤ 1 Semiconductor substrate with Si substrate 2 Wiring, 3 Interlayer insulating film 4 TiN film 5 Pt film 6 Au film 7 Al film with reverse sputtering mask 8 Resist film 9 Bonding wire

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】 半導体基板(1) 上に窒化チタン(TiN)膜
(4）, 白金(Pt)膜(5) , 金(Au)膜(6) を順に被着する工
程と, 次いで, 該Au膜(6) 上の所定領域にアルミニウム(Al)膜
(7) を形成し，該Al膜(7) をマスクにして, スパッタガ
スを用いた逆スパッタ法により該Au膜(6) 及び該Pt膜
(5) をエッチングする工程と， 次いで，該Al膜(7) をエッチング除去する工程と， 次いで, 該Au膜(6) 上にレジスト膜(8) を形成し, 該レ
ジスト膜(8) をマスクにして，該TiN 膜(4）をエッチン
グする工程と, 次いで，該基板を熱処理する工程とを有することを特徴
とする半導体装置の製造方法。1. A titanium nitride (TiN) film on a semiconductor substrate (1).
(4), a platinum (Pt) film (5), and a gold (Au) film (6) are sequentially deposited, and then an aluminum (Al) film is formed on a predetermined region of the Au film (6).
(7) is formed, the Al film (7) is used as a mask, and the Au film (6) and the Pt film are formed by a reverse sputtering method using a sputtering gas.
The step of etching (5), the step of etching away the Al film (7), and the step of forming a resist film (8) on the Au film (6) and then removing the resist film (8). A method of manufacturing a semiconductor device, comprising a step of etching the TiN film (4) using a mask, and a step of heat treating the substrate.
JP3207771A 1991-08-20 1991-08-20 Manufacture of semiconductor device Withdrawn JPH0547830A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3207771A JPH0547830A (en) 1991-08-20 1991-08-20 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3207771A JPH0547830A (en) 1991-08-20 1991-08-20 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH0547830A true JPH0547830A (en) 1993-02-26

Family

ID=16545259

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3207771A Withdrawn JPH0547830A (en) 1991-08-20 1991-08-20 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH0547830A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07106390A (en) * 1993-09-30 1995-04-21 Nec Corp Semiconductor substrate
US20210005560A1 (en) * 2019-07-01 2021-01-07 Texas Instruments Incorporated Process flow for fabrication of cap metal over top metal with sinter before protective dielectric etch

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07106390A (en) * 1993-09-30 1995-04-21 Nec Corp Semiconductor substrate
US20210005560A1 (en) * 2019-07-01 2021-01-07 Texas Instruments Incorporated Process flow for fabrication of cap metal over top metal with sinter before protective dielectric etch
US12159846B2 (en) * 2019-07-01 2024-12-03 Texas Instruments Incorporated Process flow for fabrication of cap metal over top metal with sinter before protective dielectric etch

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