JPH0472814A - Semiconductor integrated circuits and microprocessors - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and more particularly to a high-speed, low power consumption semiconductor integrated circuit comprising MOS transistors and bipolar transistors.

[Prior Art] An example of a conventional bipolar/CMOS composite (BiCMOS) logic circuit is shown in FIG. FIG. 2 shows an inverter circuit.

Two NPN bipolar transistors (
(hereinafter abbreviated as NPN) 1 and 2, PMOS transistors (hereinafter PM
(abbreviated as O8) 3 and NMOS transistor (hereinafter NMO3)
) 4. NMO85, NP connected between the base of NPNl and the GND power supply, and the gate connected to input terminal 8.
Connected between base and emitter of N2, gate is NPN
It consists of an NMO 86 connected to the base of 1. Note that 8 is an input terminal and 9 is an output terminal.

When input 8 is low level, PMO83 is on, NMO
85 is off, NPNI is on, NMO 84 is off, NMO 86 is on, and NPN2 is off. Therefore, output 9 becomes high level.

On the other hand, when input 8 is at high level, NMOS 4 is on, NMO86 is off, NPN2 is on, and PM
O83 is off, NMO85 is on, and NPNI is off. Therefore, output 9 becomes low level.

In this manner, the BjCMO5 circuit provides a logic circuit with high speed and low power consumption.

In addition, this type of BiCMOS circuit is disclosed in Japanese Patent Application Laid-open No. 1-12
No. 5021, same 1. -125022, same 1. -]25
It is disclosed in each publication of No. 023.

[Problems to be Solved by the Invention] Incidentally, in recent years, semiconductor processes have become more miniaturized, and various breakdown voltages of devices have been reduced. At the same time, the power consumption of LSI chips has increased as the scale of LSIs has increased. From this point of view, there has been a need to reduce the power supply voltage of the LST. However, if the power supply voltage Vcc is lowered to about 3V to 2.5V with the conventional configuration, Bi
It was found that the advantage 1 of the CMOSh-Tempol type disappears.

That is, as shown in FIG. 3, for example, in an inverter circuit, the dependence of the delay time tpd on the power supply voltage Vcc at a load of 0°6 pF for the CMOS totem pole type and CMOS circuit as shown in FIG. A simulation revealed that the speed of the B1CMOS totem pole type drops sharply when Vcc becomes about 2.5V. The reason for this is as follows.

In the case of the iCMOSI-TEMBALL type as shown in FIG. 2, the following equation holds true.

Vihmin=Vbe+Vth=Vccmin
-Vbe, that is, the minimum operable input high voltage Vi
hmin is the forward voltage Vbe of NPN2 and NMO84
is equal to the sum of the threshold voltage vth of NPNI-, and is equal to the minimum operable power supply voltage Vccmin minus Vbe of NPNI-. Therefore, the minimum operable power supply voltage Vccmjn is: Vccmjn=2 Vbe+ Vth=2×Q, 9+
0.6 = 2.4. (V) becomes. Therefore, when vcc becomes about 2.5V, the speed suddenly decreases.

In this way, the conventional totem pole type B as shown in Figure 2
In the iCMOS circuit, when the power supply voltage is lowered to about 3V to 2.5V, the advantages of CMOS are lost.

An object of the present invention is to maintain a speed advantage over a CMOS circuit in a heavy load section while maintaining Vcc of 3V to 2.0V.
An object of the present invention is to provide a semiconductor integrated circuit that can achieve a power supply voltage as low as about 5V.

Another object of the present invention is to provide a high-performance microprocessor using the semiconductor integrated circuit described above.

[Means for Solving the Problems] In order to achieve the above object, a semiconductor integrated circuit according to the present invention has an output terminal, a bipolar transistor and an MO
an output pull-up circuit including an S transistor and connected between a first power supply potential and the output terminal; and a bipolar transistor having a collector connected to the output terminal and an emitter connected to a second power supply potential. , a differentiating circuit for driving the bipolar transistor, and an input terminal connected to the differentiating circuit and a control terminal of the output pull-up circuit.

According to another aspect of the semiconductor integrated circuit according to the present invention, in a bipolar CMOS circuit having totem-pole connected bipolar transistors in the output stage, driving a transistor below the totem-pole connected bipolar transistors; This is performed by a differentiating circuit connected to the base of the lower transistor.

Preferably, in the semiconductor integrated circuit according to the present invention, a CMOS circuit is used in the LSI, a bipolar M○S composite circuit having the above-mentioned differential circuit is used for a heavy load section, and a CMOS circuit is used for a light load section. Use.

Preferably, the semiconductor integrated circuit or microprocessor of the present invention has a power supply terminal with an IfA value of 3.3 V or less and a power supply terminal with a ground potential, and operates between the same potentials.

As mentioned earlier, in the conventional BiCMOS1-tempole type circuit, when the power supply voltage becomes low, the base drive of the lower NPN bipolar transistor becomes weaker and the speed deteriorates significantly. In the invention, the base drive is performed by a differentiating circuit, so that the base drive does not become weak even at low power supply voltages.Therefore, even with a low power supply voltage of about 3V to 2.5V, it is possible to perform logic that is faster than a CMOS circuit in a heavy load section. A circuit can be obtained.High-speed C in light load section
By selectively using this high-speed circuit for MOS@ circuits and heavy load sections, it becomes possible to achieve even higher speeds and higher integration of LSIs.

In addition, the power consumption of this circuit is proportional to the square of the power supply voltage, but since this circuit has a low power supply voltage and consumes power only during switching, it is possible to realize a logic circuit with low power consumption. . Conversely, L to which the present invention is applied
It becomes possible to increase the scale of SI in terms of allowable power consumption. Therefore, it is possible to reduce the number of LSI chips constituting the system, and also to reduce the large delay time in the input/output interface circuit of the LSI, making it possible to realize an LSI system such as a high-performance processor.

(Hereinafter, blank spaces) [Examples] Hereinafter, various embodiments of the present invention will be described in detail with reference to the drawings.

First, FIG. 1 shows a first embodiment of the present invention.

The circuit of this embodiment is an inverter circuit. Components that are the same as those in FIG. 2 are designated by the same numbers. This inverter circuit is
NPNI,2 and NMO8],2,NP that constitute the output stage
PMO33 and NM, which control NI and take logic;
O85, a capacitor 10 connected between the input terminal 8 and the base of N I-'N2, the base of NPN2 and GN
A resistor 1] connected between D and D. PMO83 and NP
NI constitutes an output pull-up circuit.

When input 8 becomes low level, PMO83 turns on and NM
O85 is off, N I-' N l is on, N
MO312 is turned off. Further, the base potential of the NPN2 is lowered by the differentiating circuit made up of the capacitor 10 and the resistor 11, and the NPN2 is turned off.

Therefore, output 9 becomes high level. On the other hand, when input 8 becomes high level, PMO 83 is turned off, NMO 85 is turned on, NPN1 is turned off, and NM○S12 is turned on. Furthermore, the base potential of NPN2 rises due to the differentiating circuit consisting of capacitor 10 and resistor 11, and NPN2
is turned on.

Therefore, output 9 becomes low level. At this time, the charge of the load capacitance (not shown) of the output terminal 9 is
The output 9 quickly becomes a low level. Also, like the 0M08 circuit, there is no DC path, so power consumption is low.

FIG. 18 shows a cross-sectional structural diagram when the circuit of FIG. 1 is mounted on a semiconductor substrate. Parts that are the same as in FIG. 1 are designated by the same numbers. NPNI is formed in an N well 181 of a P type substrate. PMO8 is placed in the N well 182 of the P type substrate.
3 and an N-type region 1 for fixing the Vcc potential of the N well 182.
85 is formed. On the P-type substrate, NMO85,1
2 and a P required region 184 for fixing the GND potential of the P type substrate. In the N well 183, an NPN2 and a P type diffused resistor 11 are formed. Resistor 11 may be a polysilicon resistor. Below each well is an N-type buried layer. Each device is separated by a field oxide layer of 1.80 mm. A capacitor]0 made of a polysilicon film is formed on one field oxide film 180 with an insulating film interposed therebetween. The above-mentioned elements are interconnected according to the circuit diagram shown in FIG.

According to this embodiment, it is possible to realize a high-speed logic circuit with low power consumption, and as shown in FIG. 3, it has a speed advantage over the 0M08 circuit even with a low power supply voltage of about 2.5V. I can do it. In addition, instead of NMO85, NP
It is also possible to insert a resistor between the base and emitter of NI. Alternatively, the base of NPNI in the circuit of FIG.
It is also possible to add a resistor between the emitters. In those cases, the output level will be the full amplitude of the power supply voltage, so
You can do that if necessary. Furthermore, as mentioned earlier, when the input 8 falls, the base potential of NPN2 falls, so if the withstand voltage between the base and emitter of the bipolar transistor is low, a clamping voltage is applied between the base and emitter of NPN2. Just insert a diode. Although this diode is omitted in the following embodiment, it may be inserted if necessary. Also, it is clear that NOR@road etc. can be constructed based on the same idea. N.M.
O812 operates logically even if it is not present, but if it is present, DC (
(DC) stability.

Note that, as shown in FIG. 18, since NPNI and 2 have a vertical structure isolated from the P-type substrate, excellent high-speed performance can be obtained. Further, the resistor of the differential circuit may be formed of a diffusion layer or polysilicon.

Further, the capacitors of the differential circuit may be formed of polysilicon layers of different layers.

FIG. 16 shows an example of a clocked inverter constructed based on the same idea. Parts that are the same as in FIG. 1 are designated by the same numbers. P
Insert PM○5160 between MO83 and power supply potential 7,
Insert NMO8161 between NMO85 and GND,
Insert NMO8163 between O812 and GN, D, and connect NP
NMO816/l is inserted between the base and emitter of N2. A control signal φn is input to the gates of the PMO8160 and NMO8], 64, and a control signal φp is inputted to the gates of the NMO8161 and NMO163. When operating as a normal inverter, φp=n=high level and D=low level. As a result, PMO8I60 and NMO816
1 and 163 are turned on and NMO8164 is turned off, so
The equivalent circuit is shown in FIG. 1 and operates as an inverter. When operating the output as high impedance, φp is set to low level and φn is set to high level. As a result, the PMO 8160 is turned off and the base current to NPNI is cut off, so that NPNI is turned off. Also, NMO81
64 is turned on and the base potential of NPN2 becomes GND potential, so NPN2 is turned off. Furthermore, NMO3], 6
1 and 163 are turned off. Therefore, a high impedance state is formed.

A second embodiment of the invention is shown in FIG. The circuit of this embodiment takes an inverter circuit as an example. Parts that are the same as in FIG. 1 are designated by the same numbers. This inverter circuit consists of NPNI,2, diode 40 and NMO8],2,NP which constitute the output stage.
It consists of PM○S3 which controls NI, a capacitor 10 connected between the input terminal 8 and the base of NPN2, and a resistor 11 connected between the base of NPN2 and GNI').

When input 8 becomes low level, PMO33 is on and N
PNI turns on and NMO 812 turns off. Further, the base potential of the NPN 2 is lowered by the differentiating circuit made up of the capacitor 10 and the resistor 11, and the NPN 2 is turned off. Therefore, output 9 becomes high level. On the other hand, when input 8 becomes high level, PMO 83 is off and NPN
l is turned off and NMO 812 is turned on. Also, by a differentiator circuit consisting of a capacitor 10 and a resistor 11,
The base potential of NPN2 rises and NPN2 turns on. Therefore, output 9 becomes low level. At that time, the charge of the load capacitance (not shown) of the output terminal 9 is the NPN in the on state.
Since the output 9 is discharged through the diode 2 and the diode 40, the output 9 quickly becomes a low level. Also, like CMOS circuits,
There is no DC path, so power consumption is low.

=20 According to this embodiment, it is possible to realize a high-speed logic circuit with low power consumption, and even with a low power supply voltage of about 2.5 V, it is possible to provide a speed advantage over a CMOS circuit. Note that it is also possible to add a resistor between the base and emitter of NPNI. In that case, the output level will be the full amplitude of the power supply voltage, so you can do so if necessary.

Furthermore, it is obvious that a NOR circuit etc. can be constructed based on the same idea.

A third embodiment of the invention is shown in FIG. The circuit of this embodiment takes an inverter circuit as an example. Parts that are the same as in FIG. 1 are designated by the same numbers. This circuit consists of NPNI and 2. PMO83 that controls NPNI and takes logic
and NMO85, a capacitor 10. connected between input terminal 8 and the base of NPN2. NPN2 base and GND
A resistor 11 is connected between the input terminal 8 and the base of the NPN2, and the gate is connected to the output terminal 9.
Consists of MO850.

When input 8 becomes low level, PMO83 turns on and NM
O85 is off and NPNI is on.

Further, the base potential of the NPN 2 is lowered by the differentiating circuit made up of the capacitor 10 and the resistor 11, and the NPN 2 is turned off. Therefore, output 9 becomes high level. on the other hand,
When input 8 becomes high level, PMO83 turns off and NM
O85 is turned on and NPN1 is turned off. Also, by a differentiating circuit consisting of a capacitor 10 and a resistor 11, the NP
The base potential of N2 rises and NPN2 turns on. At that time, NMOS 5 remains on until output 9 falls.
A base current is also supplied through 0. Therefore, output 9
quickly becomes low level. Also, like a CMOS circuit, there is no DC path, so power consumption is low.

According to this embodiment, it is possible to realize a high-speed logic circuit with low power consumption, and even with a low power supply voltage of about 2.5 V, it is possible to provide a speed advantage over a CMOS circuit. Note that instead of the NMO 85, it is also possible to insert a resistor between the base and emitter of NPNI. Or, N.P.
It is also possible to add a resistor between the base and emitter of the NI.

In those cases, the output high level will be the full amplitude of the power supply voltage, so you can do so if necessary. Also,
NMO 81'2 shown in FIG. 1 may be added. It is obvious that a NOR circuit etc. can be constructed using a similar concept.

Further, it is also possible to similarly add the NMO 850 of FIG. 5 to that of FIG.

A fourth embodiment of the invention is shown in FIG. The circuit of this embodiment takes an inverter circuit as an example. Parts that are the same as in FIG. 1 are designated by the same numbers. This inverter circuit consists of NPNI, 2 and NMO8I2 that form the output stage, PMO83 and NMO85 that control NPN1 and take logic, NMOS 60 and capacitor 10 on the base current supply path of NPN2, and between the base of NPN2 and GND. connected resistor 1
1. Midpoint between NMOS 60 and capacitor〕O and G N
It consists of a resistor 61 connected between D and D.

When input 8 becomes low level, PMO83 turns on and NM
O85 is off and NPNI is on.

Also, NMO812 is off, NMOS60 is off,
NPN2 is turned off. Therefore, output 9 becomes high level. On the other hand, when input 8 becomes high level, PMO83
is off, NMO85 is on, and NPNI is off.

NMO 812 is turned on. Also, the NMOS 60 is turned on, and the differential circuit consisting of the capacitor 10 and the resistor 11 raises the base potential of NPN2.
is turned on. Therefore, output 9 becomes low level. At this time, the charge in the load capacitance (not shown) of the output terminal 9 is discharged through the NPN 2 in the on state, so the output 9 rapidly becomes a low level. Also, like a CMOS circuit, there is no DC path, so power consumption is low.

According to this embodiment, it is possible to realize a high-speed logic circuit with low power consumption, and even with a power supply voltage of about 2.5 V, it is possible to provide a speed advantage over a CMOS circuit. Note that instead of the NMO 85, it is also possible to insert a resistor between the base and emitter of NPNI. Or, N.P.
Base of NI = 23 It is also possible to add a resistor between the emitters.

In those cases, the output level will be the full amplitude of the power supply voltage, so you can do so if necessary.

Based on the same idea, CMOS circuits such as NAND circuits and NOR circuits
It should be clear that any circuit that can be constructed from circuits can be constructed. In addition, the NMOS shown in Fig. 5 is added to the circuit shown in Fig. 6.
It is also possible to add 50 in the same way.

FIG. 7 shows an example of a two-person NAND circuit constructed based on the same idea as FIG. 6. NPN1, 2 which constitutes the output stage, NMO8121, 12 which constitutes the output stage and takes logic.
2. PMO33 that drives NPNI and takes logic
],,32. NMO862, 63 on the base current supply path of NMO851, 52, NPN2, capacitor 10, and resistor 1 connected between the base of NPN2 and GND.
1°, midpoint between NMO863 and capacitor 10 and GND
It consists of a resistor 61 connected between.

When input 8] or 82 is low level, 2MO83
1 or 32 is on, NMO351 or NMO8
52 is off, NPNI is on, NMO8121
Or NMO8122, NMO862 or NM
, 0863 are turned off.

Therefore, the output level quickly becomes high.

On the other hand, when inputs 81 and 82 are both high level, PMO
531 and 32 are turned off, NMO551 and NMOS52 are turned on, NPNI is turned off, and NMO8121 and 122 are turned on. Also, NMOS62 and 63 are turned on,
A differential circuit consisting of a capacitor 10 and a resistor 11 raises the base potential of NPN2, turning on NPN2. Therefore, output 9 becomes low level. At this time, the charge of the load capacitance (not shown) of the output terminal 9 is
Since it is discharged through N2, the output 9 quickly becomes a low level. Also, like a CMOS circuit, there is no DC path, so power consumption is low.

According to this embodiment, it is possible to realize a high-speed logic circuit with low power consumption, and even with a low power supply voltage of about 2.5 V, it is possible to provide a much superior speed over a CMOS circuit.

In addition, instead of NMO851 and 52, N1)
It is also possible to insert a resistor between the base and emitter of. Alternatively, it is also possible to add a resistor between the base and emitter of the NPNI. In those cases, the output level will be the full amplitude of the power supply voltage, so you can do so if necessary.

It is also possible to add the NMO 850 shown in FIG. 5 to the circuit shown in FIG. 7 in the same way. NMO8 in Figure 9, which will be described later.
90 could be added to the circuit of FIG. 7 as well.

A fifth embodiment of the invention is shown in FIG. The circuit of this embodiment takes an inverter circuit as an example. Parts that are the same as in FIG. 1 are designated by the same numbers. This circuit consists of NPNI that constitutes the output stage.
, 2, and NMO3i2, PMO83 and NMO35 that control NPNI and take logic, NMO3170 and capacitor 10 on the base current supply path of NPN2,
Resistor 11, N connected between the base of NPN2 and GND
It consists of a resistor 6 connected between the midpoint of the MO8170 and the capacitor 1o and GND.

When input 8 becomes low level, PMO83 turns on and NM
O85 is off and NPNI is on.

Also, when NMO812 is off and NMO8170 is off,
NPN2 is turned off. Therefore, the output level 9 becomes high level. On the other hand, when input 8 becomes high level, PM
O83 is off, NMO85 is on, and NPNI is off. NMO8], 2 is turned on. Also, NMO81
70 is turned on, the base potential of NPN2 rises due to the differentiator circuit consisting of capacitor]0 and resistor 11,
NPN2 turns on. Therefore, output 9 becomes low level. At this time, the charge in the load capacitance (not shown) of the output terminal 9 is discharged through the NPN 2 in the on state, so the output 9 rapidly becomes a low level. Also, like the 0M08 circuit, there is no DC path, so power consumption is low.

According to this embodiment, it is possible to realize a high-speed logic circuit with low power consumption, and even with a low power supply voltage of about 2.5V, it is possible to provide a speed advantage over the 0M08 circuit. Note that instead of the NMO 35, it is also possible to insert a resistor between the base and emitter of NPNI. Or, N
It is also possible to add a resistor between the base and emitter of the PNI.

In those cases, the output level will be the full amplitude of the power supply voltage, so you can do so if necessary.

It is clear that all circuits that can be constructed with CMOS circuits, such as NAND circuits and NOR circuits, can be constructed using the same idea.

It is also possible to similarly add the NMO 850 shown in FIG. 5 to the circuit shown in FIG. 17. Furthermore, it is also possible to similarly add an NMO 890 shown in FIG. 9, which will be described later, to the circuit shown in FIG. 17. In addition, in the circuit of FIG. 17, NMO81
Even without 2, it is stable in terms of DC.

A sixth embodiment of this embodiment is shown in FIG. The circuit of this embodiment takes an inverter circuit as an example, and is a combination of the configurations of FIGS. 4 and 6. Components that are the same as those in FIGS. 4 and 6 are designated by the same numbers. This circuit consists of NPN that constitutes the output stage.
I, diode 40 and NP N 2, NMO312, N
PMO33 that controls PNI, NMOS 60 and capacitor 10 in the base current supply path of NPN2. N
Resistor 11, NM connected between the base of PN2 and GND
It consists of a resistor 61 connected between the midpoint between O360 and capacitor 10 and GND.

When input 8 becomes low level, PMO 83 is on and N
PNI is turned on. Also, NMO8I2 is off, NM
OS 60 is off and NPN2 is off. Therefore,
Output 9 becomes high level.

On the other hand, when input 8 becomes high level, PMO 83 is turned off and NPNI is turned off. NMO31,2 is turned on. Also, NMOS 60 turns on and capacitor 10
The base potential of NPN2 is doubled by the differentiating circuit consisting of the resistor 11 and the resistor 11, and NPN2 is turned on. Therefore,
Output 9 becomes low level. At this time, the charge in the load capacitance (not shown) of the output terminal 9 is discharged through the NPN 2 in the on state, so the output 9 rapidly becomes a low level. Also, like the 0M08 circuit, there is no DC path, so power consumption is low.

According to this embodiment, it is possible to realize a high-speed logic circuit with low power consumption, and even with a low power supply voltage of about 2.5 V, it is possible to provide a speed advantage over a CMOS circuit. Note that it is also possible to add a resistor between the base and emitter of NPNI. In that case, the output level will be the full amplitude of the power supply voltage, so you can do so if necessary.

With the same idea, N A N Dl circuit, NOR circuit, etc.
It will be clear that any circuit that can be constructed from MOS circuits can be constructed.

Further, it is also possible to similarly add the NMO 850 of FIG. 5 to FIG.

A seventh embodiment of the invention is shown in FIG. The circuit of this embodiment takes an inverter circuit as an example. Parts that are the same as in FIG. 1 are designated by the same numbers. This circuit consists of the NPNI and 2 that make up the output stage, and the PMO83 that controls the NPNI and takes logic.
and NMO85, a capacitor 10 connected between the input terminal 8 and the base of NPN2, and the base of NPN2 and GND.
It consists of a resistor 11 connected between them and an NMO 890 that controls the NPN 2 and takes logic. When input 8 becomes low level, PMO83 is on, NMO85 is off, and N
PNI is turned on. Also, when NMO890 is off, the differentiating circuit consisting of capacitor 10 and resistor 11
The base potential of NPN2 drops and NPN2 is turned off. Therefore, output 9 becomes high level. On the other hand, when input 8 becomes high level, PMO 83 is turned off, NMO 85 is turned on, and NPNI is turned off. Also, capacitor 10
The base potential of NPN2 is increased by the differentiating circuit consisting of and resistor 11, and NPN2 is turned on. At that time, the base current is also supplied through the NMO 390 which is in the on state. Therefore, the output 9 quickly becomes a low level. Also,
Like CMOS circuits, there is no DC path, so power consumption is low.

According to this embodiment, it is possible to realize a high-speed logic circuit with low power consumption, and even with a low power supply voltage of about 2.5 V, it is possible to provide a speed advantage over a CMOS circuit. Note that instead of the NMO 85, it is also possible to insert a resistor between the base and emitter of NPNI. Alternatively, it is also possible to add a resistor between the base and emitter of the NPNI.

In those cases, the output level will be the full amplitude of the power supply voltage, so you can do so if necessary.

It is clear that all circuits that can be constructed with CMOS circuits, such as NAND circuits and NOR circuits, can be constructed using the same idea.

It is also possible to add the NMO 890 of FIG. 9 to FIG. 4 in the same way. Note that since the NMO 890 is provided, the NMO 312 in FIG. 1 is unnecessary in this embodiment.

An eighth embodiment of the present invention is shown in FIG. The circuit of this embodiment takes an inverter circuit as an example, and is a combination of the configurations of FIGS. 6 and 9. Components that are the same as those in FIGS. 6 and 9 are designated by the same numbers. NPNI and 2, NP that constitute the output stage
PMO83 and NMO control NI and take logic
85, NMO8 on the base current supply bus of NPN2
60 and capacitor 1. Resistor 11 connected between the base of O, NPN2 and GND, Resistor 61 connected between the midpoint of NMOS 60 and capacitor 10 and GND, NPN
It is composed of an NMOS 90 that controls 2 and also takes logic.

When input 8 becomes low level, PMO83 turns on and NM
O85 is off and NPNI is on.

Also, NMO860 is off, NMO390 is off, and NMO860 is off.
PN2 is turned off. Therefore, output 9 becomes high level. On the other hand, when input 8 becomes high level, PMO 33 is turned off, NMO 35 is turned on, and NPNI is turned off. Further, the NMO 860 is turned on, and the base potential of the NPN2 is increased by the differentiating circuit made up of the capacitor 10 and the resistor 11, and the NPN2 is turned on. At that time, the base current is also supplied through the NMO 890 which is in the on state.

Therefore, the output 9 quickly becomes a low level. Also, CM
Like the OS circuit, there is no DC path, so power consumption is low.

According to this embodiment, it is possible to realize a high-speed logic circuit with low power consumption, and even with a low power supply voltage of about 2.5 V, it is possible to provide a speed advantage over a CMOS circuit. Note that instead of NM and O85, it is also possible to insert a resistor between the base and emitter of NPN. or,
It is also possible to add a resistor between the base and emitter of the NPNI.

In those cases, the output level will be the full amplitude of the power supply voltage, so you can do so if necessary.

(Hereinafter, blank spaces) Based on the same idea, it is clear that all circuits that can be constructed with CMOS circuits, such as NAND circuits and NOR circuits, can be constructed.

It is also possible to add the NMO 890 of FIG. 10 to the circuit of FIG. 8 in the same way.

A ninth embodiment of the present invention will be described with reference to FIG. This embodiment takes an inverter circuit as an example. Parts that are the same as in FIG. 1 are designated by the same numbers. The difference from FIG. 1 is that a base bias is applied to NPN2.

NPNI, 2 and NMO812, NPN that constitute the output stage
PMO83 and 8MO8 control I and take logic
5. Capacitor 10 connected between input terminal 8 and the base of NPN2. Resistor 11 connected between the base of NPN2 and GND, NP that biases the base potential of NPN2
Consists of NIIO. The base of NPNI 10 is NPN
It is connected to a reference potential 111 that sets the base potential of No. 2.

Let the potential of the reference potential 111 be vR, and the NPN at bias
If the base potential of 2 is VB, then vR is.

VR=VB+VBII (NPNIIO) is given.

When input 8 becomes low level, PMO83 turns on and 8M
O85 is off, NPNl is on, NMO812
is turned off. In addition, the base potential of NPN2 is lowered by the differentiating circuit consisting of the capacitor 10 and the resistor 11,
NPN2 is turned off.

Therefore, output 9 becomes high level. On the other hand, when input 8 becomes high level, PMO 83 is turned off, 8MO 85 is turned on, NPNI is turned off, and NMO 812 is turned on. Further, the base potential of the NPN 2 rises from the base bias potential by the differentiating circuit consisting of the capacitor 10 and the resistor 11, and the NPN 2 is rapidly turned on. Therefore, output 9 becomes low level. At that time, the charge on the load capacitor (not shown) at the output terminal °9 rapidly turns on.
2, the output 9 quickly becomes a low level.

According to this embodiment, since a bias current flows, the power consumption is slightly large, but a high-speed logic circuit can be realized, and 2.5
Even with a power supply voltage as low as V, it is possible to provide a speed advantage over the CM○S circuit. In addition, 8MO85
Instead, it is also possible to insert a resistor between the base and emitter of NPN1. Alternatively, it is also possible to add a resistor between the base and emitter of the NPNI. In those cases, the output level will be the full amplitude of the power supply voltage, so you can do so if necessary. Also, NMO8
12, the logic operates even if it is not present, but if it is present, it becomes stable in terms of DC.

It is obvious that a NOR circuit or the like can also be constructed based on the same idea.

Furthermore, in FIG. 11, a base bias is applied to the circuit of FIG. 1, but the circuits described so far can be biased using a similar biasing method.

A tenth embodiment of the present invention will be described with reference to FIG. The circuit of this embodiment takes an inverter circuit as an example. Parts that are the same as those in FIG. 11 are designated by the same numbers. The difference from Figure 11 is NP.
The point is that a base bias is applied to NI as well. This circuit consists of NPNI, 2 and NMO812, NP which constitute the output stage.
PMO83 and NM control NI and take logic
OS 5, capacitor 10 connected between input terminal 8 and the base of NPN2, 1 between the base of NPN2 and GND
N P N ], which biases the base potentials of the resistor 11, bias resistor 126, and NPN1 and NPN2 connected intermittently; 1.
Consists of 0. The base of NPNl 10 is NPNI and 2
It is connected to a reference potential 1'1 which sets the base potential of .

When input 8 becomes low level, PMO83 turns on and NM
As O85 turns off and the base potential of NPNI rises from the bias potential, NPNI quickly turns on.

NMO 812 is turned off.

Further, the base potential of the NPN 2 is lowered by the differentiating circuit including the capacitor 10 and the resistor 1, and the NPN 2 is turned off. Therefore, output 9 quickly becomes high level. On the other hand, when input 8 becomes high level, PMO33 turns off.
NMO85 is on, NPNI is off, NMO8
], 2 is turned on. Also, capacitor 10 and resistor 11
By the differentiator circuit consisting of, the base potential of NPN2 is
It rises from the base bias potential and NPN2 turns on rapidly. Therefore, output 9 becomes low level.

At this time, the charge in the load capacitance (not shown) of the output terminal 9 is discharged via the NPN 2 which rapidly turns on, so that
Output 9 quickly becomes low level.

According to this embodiment, since a bias current flows, the power consumption is slightly large, but a high-speed logic circuit can be realized, and 2.5
Even with a power supply voltage as low as V, it is possible to provide a speed advantage over a CMOS circuit.

Note that it is also possible to add a resistor between the base and emitter of NPNI. In that case, the output level will be the full amplitude of the power supply voltage, so you can do so if necessary. Further, although the NMOs 81 and 2 operate logically even if they are not present, if they are present, they become stable in terms of DC.

It is obvious that a NOR circuit or the like can also be constructed based on the same idea.

Further, in FIG. 12, a base bias is applied to the circuit of FIG. 1, but the circuit described so far can be biased by a biasing method similar to 39.

An eleventh embodiment of the present invention is shown in FIG. The circuit of this embodiment is the circuit of FIG. 6 with a base bias applied. Parts that are the same as those in FIG. 6 are designated by the same numbers. The difference from FIG. 6 is that base bias is applied to NPNI and 2. N1) Nl,2 and NMO81,2 that constitute the output stage
, PMO83 and NMO35 that control NPNI and take logic, NMOS60 and capacitor 10 in the base current supply path of NPN2, base of NPN2 and G
Resistor 11 connected between NMO860 and capacitor 10, and Resistor 61 connected between GND and GND.
I) NPN133 with N1 base bias;
Resistors 134, 135 and CMOS inverter 136, NP
NPN130, resistor 13 for base bias of N2
Consists of 1.

When input 8 becomes low level, PMO33 turns on and NM
O85 is off and NPN3 is on.

Also, NMO 812 is off, NMOS 60 is off, and N I? N2 is turned off. NPN turned on
Since the base potential of I rises from the bias potential, NP
NI turns on quickly. Therefore, output 9 quickly becomes high level. On the other hand, when input 8 becomes high level, P
MO83 is off, NMO85 is on, and NPNI is off. NMO 812 is turned on. Also, NMOS
60 is turned on, the differential circuit consisting of capacitor 10 and resistor 11 raises the base potential of NPN2, and NPN
PN2 turns on. Therefore, output 9 becomes low level. At this time, the charge in the load capacitance (not shown) of the output terminal 9 is discharged through the NPN 2, which rapidly turns on due to its base bias, so that the output 9 quickly becomes a low level.

According to this embodiment, since a bias current flows, the power consumption is slightly large, but a high-speed logic circuit can be realized, and 2.5
Even with a power supply voltage as low as V, it is possible to provide a speed advantage over a CMOS circuit. Further, a power supply circuit for generating a reference potential for base bias becomes unnecessary. Note that it is also possible to add a resistor between the base and emitter of the NPNJ. In that case, the output level will be the full amplitude of the power supply voltage, so you can do so if necessary.

Based on the same idea, CMOS circuits such as NAND circuits and NOR circuits
It should be clear that any circuit that can be constructed from circuits can be constructed.

Furthermore, in FIG. 13, a base bias is applied to the circuit of FIG. 6, but the circuits described so far can be biased using a similar biasing method.

A twelfth embodiment of the present invention is shown in FIG. This circuit is an example of a macrocell, and a CMOS inverter 320, B ]CMO which inherits the latch circuit and holds data.
It consists of an S inverter 321, a CMo5t to transfer gate 323, a CMOS inverter 322 that generates an inverted signal of the latch pulse, and a CMO51 to transfer gate 1-324 that controls passing/not passing D in. B
As the jCMOS inverter 321, the one described above may be used. When manually controlling Djn, the latch pulse T is set to high level. As a result, the 1-Lance Sphere gate 324 is turned on and the 1-Lance Sphere gate 323 is turned off. Then, the level of D out becomes the level of Djn. After that, the latch pulse T is set to low level.

Then, the transfer gate 324 turns off, transfer gates 1 to 1 to 323 turn on, and the CMOS inverter 3
20. Bj CMOS inverter 321 and CMOS+
-Lancefage-1-323 holds data. CM
The OS circuit is fast under light loads, and the BiCMOS circuit is fast under heavy loads, so if you use CMOS circuits and BicMO8 circuits differently in this way, you can create a high-speed macrocell with a small area. According to this embodiment, the power consumption is low and the area efficiency is good.

Even with a power supply voltage as low as 2.5 .ANG., it is possible to realize a macro cell that has a speed advantage over CMOS circuits.

A thirteenth embodiment of the present invention is shown in FIG. In the figure, 330 is an LSI chip, 331 is a BiCMOS logic circuit shown in the embodiment of the present invention, 332 is a macro cell shown in the embodiment of the present invention, and 333 is a normal CMOS logic circuit. As shown in Figure 20, the CMOS circuit has a load C
The BiCMOS circuit is fast when the load CL is light, and the BiCMOS circuit is fast when the load CL is heavy.
．． Set it to 3V or less. The power consumption of the circuit explained so far is proportional to the square of Vcc, excluding the base bias current, so by lowering Vcc, the LSI chip 3
30 power consumption can be significantly reduced. In other words, it is possible to improve the degree of integration up to the permissible power consumption.

Therefore, it is possible to reduce the number of LSI chips constituting the system, and the large delay time in the input/output interface circuit of the LSI can be reduced.

In addition, the BiCMOS circuit of the present invention can be used as a CMOS circuit even at low power supply voltages where Vcc is about 3°3 to 2.5 cm.
It has a speed advantage over circuits. Therefore, according to this embodiment, the LS of a high-performance microprocessor, etc.
I system can be realized.

A fourteenth embodiment of the present invention is shown in FIG. This figure shows the general configuration of an electronic computer, in which a central processing unit CPU (Centra) is connected via a bus 190.
ssjng Unjt), memory for storing data exchanged with this CPU, memory controller, I10
Processor is connected. In this system,
For example, taking a CPU as an example, the logic circuit used in the CPU is required to have high-speed performance in order to perform calculations at high speed. On the other hand, if this CPU is divided into several LSI chips, the propagation delay time of signals between LSIs will increase, and system performance will not improve, so it is necessary to increase the scale of the LSI. However, as LSIs become larger in scale, power consumption increases, so logic circuits with low power consumption become essential. Therefore, since the logic circuit described above has high speed and low power consumption, if this logic circuit is applied to a microprocessor or the like in the manner shown in FIG. 15, a high-performance system 11 can be constructed.

According to this embodiment, it is possible to realize a high-performance microprocessor or the like having twice the performance of CMOS.

[Effects of the Invention] According to the present invention, since a differential type BjCMOS composite circuit with little speed deterioration even at a low power supply voltage is used, Vcc=
Even with a low power supply voltage of about 2.5V, Speed I- has an advantage over CMOS circuits in heavy loads, and has low power consumption.
This has the effect of realizing a high-speed logic circuit. Furthermore, by using this logic circuit, it is possible to improve the overall performance of I and SI. In addition, even with a low power supply voltage of about 2.5 V, it has an advantage of speed 1 or higher in heavy load sections compared to CMOS circuits, so LS to which this circuit is applied
It becomes possible to lower the power supply voltage of I and to use it with a CMOS circuit, making it possible to increase the scale of LSI chips in terms of power consumption and circuit occupation area. Therefore, using this circuit,
I/ST systems such as high-performance processors can be realized.

[Brief explanation of the drawing]

Figure 1 is a BjCMOS composite inverter circuit diagram according to the first embodiment of the present invention, Figure 2 is a conventional BiCMOS composite inverter circuit diagram, and Figure 3 is a simulation of power supply voltage dependence of delay time of various logic circuits. A graph showing the results, FIG. 4 is a Bj and CMOS composite inverter circuit diagram of the second embodiment of the present invention, and FIG. 5 is a Bi of the third embodiment of the present invention.
A CMOS composite inverter circuit diagram, FIG. 6 is a BiCMOS composite inverter circuit diagram according to the fourth embodiment of the present invention, and FIG. 7 is a BiCMOS composite inverter circuit diagram according to the fourth embodiment of the present invention.
Human power NAND circuit diagram, Figure 8 is a BjCMOS composite inverter circuit diagram of the sixth embodiment of the present invention, Figure 9 is a BiCMOS composite inverter circuit diagram of the seventh embodiment of the present invention, and Figure 10 is the present invention. FIG. 11 is a BiCMOS composite inverter circuit diagram of the eighth embodiment of the invention, FIG. 12 is a BjCMOS composite inverter circuit diagram of the ninth embodiment of the invention, and FIG. 12 is a BiCMOS composite inverter circuit diagram of the tenth embodiment of the invention. The inverter circuit diagram in FIG. 13 is the BjCM of the eleventh embodiment of the present invention.
The inverter circuit diagram of the OS combination, FIG. 14, is the first inverter circuit diagram of the present invention.
BiCMOS composite latch circuit diagram of Example 2, No. 15
The figure shows B] CMOS composite LS of the thirteenth embodiment of the present invention.
The configuration diagram of the I chip, FIG. 16, is a BiCMOS which is an application of the embodiment shown in FIG. 17 is a circuit diagram of a BiCMOS composite inverter according to the fifth embodiment of the present invention, and FIG. 18 is a circuit diagram of a BiCMOS composite inverter of the fifth embodiment of the present invention.
A cross-sectional structural diagram of a composite inverter circuit mounted on a semiconductor substrate, FIG. 19 is a configuration diagram of a computer system according to a fourteenth embodiment of the present invention, and FIG. 20 is a diagram of a CMOS circuit and a B: iCMOS circuit of the present invention. It is a graph showing load dependence of delay time. 1.2...NPN bipolar transistor, 3PMO
8 + - transistor, 5.12...NMOS transistor, 10 capacitor, "" Resistor, 60.1, 70.
・NMOS transistor, 330...LSI chip.

Claims (1)

[Claims] 1. An output terminal, an output pull-up circuit including a bipolar transistor and a MOS transistor and connected between a first power supply potential and the output terminal, and a collector connected to the output terminal. , a bipolar transistor whose emitter is connected to a second power supply potential, a differentiating circuit for driving the bipolar transistor, and an input terminal connected to the differentiating circuit and a control input terminal of the output pull-up circuit. A semiconductor integrated circuit characterized by: 2. an output terminal; an output pull-up circuit including a bipolar transistor and a MOS transistor and connected between a first power supply potential and the output terminal; a collector connected to the output terminal and an emitter connected to a second power supply potential; a bipolar transistor connected to the bipolar transistor, a differentiating circuit that drives the bipolar transistor, an NMOS transistor whose channel is connected between the differentiating circuit and the first power supply potential, and a gate of the NMOS transistor and the output pull A semiconductor integrated circuit comprising: a control terminal of an up circuit; and an input terminal connected to the control terminal. 3. an output terminal; an output pull-up circuit including a bipolar transistor and a MOS transistor and connected between a first power supply potential and the output terminal; a collector connected to the output terminal and an emitter connected to a second power supply potential; a bipolar transistor connected to the bipolar transistor, a differentiator circuit that drives the bipolar transistor, an NMOS transistor whose channel is connected between the differentiator circuit and the output terminal, and a gate of the NMOS transistor and the output pull-up circuit. A semiconductor integrated circuit comprising: a control terminal; and an input terminal connected to the control terminal. 4. The output pull-up circuit includes a bipolar transistor whose collector is connected to the first power supply potential and whose emitter is connected to the output terminal, and a channel between the base of the bipolar transistor and the first power supply potential. and a PMOS transistor whose gate is connected to the input terminal.
, 2 or 3. The semiconductor integrated circuit according to . 5. A first bipolar transistor whose collector is connected to a first power supply potential and whose emitter is connected to an output terminal, and a channel is connected between the base of the first bipolar transistor and the first power supply potential. a PMOS transistor whose gate is connected to the input terminal thereof; a diode whose anode and cathode are connected to the emitter and base of the first bipolar transistor, respectively; and a collector whose collector is connected to the cathode of the diode and which is connected to a second power supply potential. A second bipolar transistor having an emitter connected to the second bipolar transistor, and a differentiating circuit connected between the base of the second bipolar transistor and the input terminal to drive the second bipolar transistor. Semiconductor integrated circuit. 6. In a bipolar CMOS circuit having totem-pole connected bipolar transistors in the output stage, a differential circuit connected to the base of the lower transistor drives the lower transistor of the totem-pole connected bipolar transistor. A semiconductor integrated circuit characterized by being operated by. 7. Claim 1, 2, 3, 5 or 6, wherein the differentiating circuit comprises a resistor and a capacitor, further comprising an NMOS transistor having a channel connected to the capacitor and a gate connected to the output terminal. The semiconductor integrated circuit described. 8. Claim 1, 2, 3 or 8, further comprising an NMOS transistor whose channel is connected between the collector and base of the bipolar transistor driven by the differentiating circuit and whose gate is connected to the input terminal. 5. The semiconductor integrated circuit according to 5. 9. A first bipolar transistor whose collector is connected to a first power supply potential and whose emitter is connected to an output terminal, and a channel is connected between the base of the first bipolar transistor and the first power supply potential. a PMOS transistor whose gate is connected to the input terminal; a diode whose anode and cathode are connected to the emitter and base of the first bipolar transistor, respectively; and a collector whose collector is connected to the cathode of the diode and which is connected to a second power supply potential. a second bipolar transistor having an emitter connected to the second bipolar transistor, a differentiating circuit for driving the second bipolar transistor, a channel being connected between the differentiating circuit and the first power supply potential, and having a gate connected to the input terminal. A semiconductor integrated circuit comprising a connected NMOS transistor. 10. The semiconductor integrated circuit according to claim 1, further comprising base bias means for applying a base bias to the bipolar transistor. 11. The semiconductor integrated circuit according to claim 1, 2, 3, 5, 6, or 9, wherein the resistor constituting the differential circuit is a diffusion layer resistor. 12. The semiconductor integrated circuit according to claim 1, 2, 3, 5, 6, or 9, wherein the resistor constituting the differential circuit is a polysilicon resistor. 13. The semiconductor integrated device according to claim 1, 2, 3, 5, 6, or 9, wherein the capacitor constituting the differential circuit is a capacitor formed between different polysilicon layers with an insulating layer in between. circuit. 14. The semiconductor integrated circuit according to claim 1, 2, 3, 5, 6, or 9, wherein the bipolar transistor has a vertical structure isolated from a P-type substrate. 15. Claim 1, 2, 3, 5, 6 or 9, characterized in that it has a power supply terminal whose absolute value is 3.3V or less and a power supply terminal whose absolute value is a ground potential, and operates between the two potentials.
The semiconductor integrated circuit described. 16. Claims 1, 2, 3, 5, used for a heavy load section.
10. A semiconductor integrated circuit comprising the semiconductor integrated circuit according to 6 or 9 and a CMOS circuit used for a light load section. 17. Claims 1 and 2, in which the device operates between a power supply terminal having a potential whose absolute value is 3.3 V or less and a power supply terminal having a ground potential.
10. A microprocessor comprising the semiconductor integrated circuit according to 3, 5, 6 or 9.