JPH0473608B2 - - Google Patents

Description

Detailed Description of the Invention (Industrial Application Field) The present invention relates to the manufacture of semiconductor devices having alignment marks for aligning masks and wafers in the photolithography process of semiconductor device manufacturing processes. Regarding the method.

(Prior Art) Conventionally, in the alignment method using a monochromatic light source for illumination, the conventional alignment mark is LOCOS (Local oxidation of
A mark shape 1 is formed by a silicon process, a film to be etched is formed in a subsequent process, and a resist is coated on this film to be etched.
This is overlapped with mark 2 on the mask and scanned in the direction from to' to perform alignment.

FIG. 4 is a sectional view taken along the -' line in FIG.
As is clear from this figure, a field oxide film 4 is formed on a Si substrate 3, and this field oxide film 4 is
A gate oxide film 5 is formed in between, and furthermore, a film to be etched 6 and a resist film 7 are successively formed.

Here, 8a and 8b correspond to both ends of the gate oxide film 5, and 9a and 9b correspond to the edges (surroundings) of the mask.

(Problem to be Solved by the Invention) However, in the alignment mark having the above configuration, the thicknesses of the field oxide film 4, the film to be etched 6, and the resist film 7 vary minutely due to interference between the multilayer thin films during alignment. Then, the reflectance from the wafer alignment mark becomes extremely small, making the alignment mark invisible.
I had a problem where alignment became impossible.

The present invention eliminates the above problems and provides a semiconductor device having an alignment mark that always has high edge contrast and allows highly accurate alignment even when the thickness of each thin film constituting the wafer alignment mark portion changes. The purpose is to provide a manufacturing method.

(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention provides a method for manufacturing a semiconductor device that includes a gate formation step of patterning a gate oxide film. The mark shape is formed using a field oxide film, and at that time, the area in contact with the reticle mark is made into a field oxide film, and then, in the process of etching the gate oxide film, a line and space pattern (irregularities) is etched parallel to the scanning line. The thickness of the field oxide film and the gate oxide film are alternately changed, and an opaque gate electrode material is applied thereon.

Further, after the gate forming step, the gate electrode material is left on the wafer alignment mark portion.

(Function) According to the present invention, the mark shape used for alignment in the gate forming step is formed using a field oxide film, the region in contact with the reticle mark is made into a field oxide film, and then the gate oxide film is etched. In the process, a line-and-space pattern was formed by etching parallel to the scanning line, and the thickness of the field oxide film and gate oxide film was alternately changed, so that an opaque film was formed on top of the field oxide film. The edge contrast with the mask is high, allowing highly accurate alignment between the wafer and the mask.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a plan view of a semiconductor device having an alignment mark according to the present invention, and FIG.
FIG.

In the figure, 11 is the mask alignment mark, 1
2 is the alignment mark part of the wafer, 13 is the background part of the wafer alignment mark, 14 is the periphery of the mask, and A and B are the presence or absence of patterning during patterning of the first gate oxide film, that is, the presence or absence of patterning of the gate oxide film. A portion A that was etched in the etching process and a portion B that was not etched are shown. Further, 15 and 16 indicate two points on the edge (periphery) of the mask.

Here, the method for forming alignment marks will be explained in detail based on FIG. 2.

First, as shown in FIG. 2a, a field oxide film 22 is formed in the shape of a mark on a silicon (Si) substrate 21. As shown in FIG.

Next, as shown in FIG. 2b, a gate oxide film 23 is formed between the field oxide films 22.

Next, in order to pattern the gate oxide film 23, a resist is applied, a resist film 24 is formed, and patterning is performed as shown in FIG. 2c. At this time, the gate oxide film 23 and the field oxide film 22 form a line-and-space (unevenness) pattern parallel to the scanning line used for alignment.

Next, as shown in FIG. 2d, the gate oxide film 23 and field oxide film 22 are etched, and the resist film 24 (see FIG. 2c) is removed. At this time, it is preferable that the field oxide film 22 be etched by about 650 Å using the G line of a mercury lamp.

Next, as shown in FIG. 2e, an opaque film 25 made of a gate electrode material such as polycide, silicide, or metal is formed, and a resist is further applied to form a resist film 26. In this state, alignment in the gate formation process is performed.

In this way, the field oxide film 22, which has an alignment mark shape formed parallel to the scanning line, is configured to have a film thickness difference using a line-and-space pattern when etching the gate oxide film 23. An opaque gate electrode material such as polycide, silicide, or metal, which is considered to be a substrate, is formed on the substrate, and a resist is applied to the surface.The resist is applied to a flat surface regardless of whether the top or bottom is stepped. Therefore, optically, the difference in structure between the part etched in the etching process of the gate oxide film in the region in contact with the reticle mark and the part not etched is due to the step difference in the field oxide film 22 when the gate oxide film 23 is etched. This is the difference in resist film thickness.

Furthermore, the period of change in reflectance due to change in resist film thickness is approximately 1300 Å when using a mercury lamp, and if the step difference during gate oxide etching of the field oxide film is set to approximately 650 Å, Due to the difference in resist film thickness at the top and bottom of the step, the field oxide film has a structure in which the phase of the reflectance at the top and bottom of the step is shifted by about half a phase.

With this configuration, the resist film 2
Even if the film thickness of 6 varies, the upper part of the step of the field oxide film due to etching of the gate oxide film,
The lower portion will always have wafer alignment marks with high edge contrast compared to the edges (surroundings) of the mask. Therefore, by forming the line-and-space (unevenness) pattern of the gate oxide film 23 and the field oxide film 22, alignment between the wafer and the mask can be ensured in comparison with the edges of the mask. That is, if the line and space (unevenness) is not formed, there is no contrast with the edge of the mask, and alignment between the wafer and the mask may not be possible, but according to the present invention, the line and space (unevenness) is not formed. This can be completely eliminated by forming and spaces (unevenness).

Next, a second embodiment of the present invention will be described based on FIG.

In the figure, 31 is a silicon substrate, 32 is a field oxide film, 33 is a gate oxide film, 34 is an opaque gate electrode material, 35 is a film to be etched, 36
is a resist film.

In this embodiment, the gate electrode material 34 is left as is and is used as an alignment mark after the gate formation process. In other words, in the step e in FIG. 2 described above, the alignment mark that was not used for mask alignment is left without removing the gate electrode material 34, so that the area below the gate electrode material 34 is not visible, and the gate electrode material 34 is Allow it to be treated as the upper membrane.

With this configuration, even if the film thicknesses of the film to be etched 35 and the resist film 36 vary, the upper and lower steps of the field oxide film 32 caused by etching the gate oxide film 33 will always form wafer alignment marks with high edge contrast. will have the following.

Next, a third embodiment of the present invention will be described based on FIG. 6.

First, alignment marks are formed. That is, as shown in FIG. 6a, the silicon substrate 4
1, a first gate oxide film 42, then a polysilicon first gate film 43, and then a second gate oxide film 44 are formed. In this case, indicates the mark portion, and indicates the background portion.

Next, as shown in FIG. 6b, unevenness is formed. At this time, a contact hole is formed in the second gate oxide film 44.

Next, as shown in FIG. 6c, an opaque film 45 which is a gate electrode material is formed.

Note that if the resist film is formed so that there are no unevenness on the surface, the difference in the thickness of the resist film will depend on the unevenness of the oxide film, so if the unevenness of the oxide film is 650 Å, It is desirable because it becomes 650 Å as it is.

Further, the present invention can be used for any alignment mark, and there is no need to change conventional wafer manufacturing equipment or processes.

Note that the present invention is not limited to the above-mentioned embodiments, and various modifications can be made based on the spirit of the present invention, and these are not excluded from the scope of the present invention.

(Effects of the Invention) As explained in detail above, according to the present invention,
A method for manufacturing a semiconductor device including a gate forming step of patterning a gate oxide film, which includes a step of forming a field oxide film in a mark shape on a silicon substrate, a step of forming a gate oxide film between the field oxide films, and a resist. forming a film and patterning the resist film; using the patterned resist film as a mask, etching the field oxide film and the gate oxide film to remove the patterned resist film; The steps of forming an uneven pattern parallel to the scanning line for alignment on the oxide film and the gate oxide film, patterning the gate oxide film, and forming an opaque film are sequentially performed. (1) Even if the thickness of each thin film constituting the wafer alignment mark portion changes, it is possible to always obtain a wafer alignment mark with high edge contrast with the mask.

(2) Interference can be calculated using only the resist thickness, making it easier to create contrast differences.

(3) The line and space formation is performed simultaneously with the patterning of the gate oxide film, that is, the formation of contact holes, so the process does not become complicated.

Therefore, with a simple configuration, it is possible to significantly improve the alignment accuracy between the wafer and the mask.

[Brief explanation of the drawing]

FIG. 1 is a plan view of a semiconductor device having a wafer alignment mark according to the present invention, FIG. 2 is a manufacturing process diagram taken along the line -' in FIG. 1, and FIG. 3 is a plan view of a semiconductor device having a conventional wafer alignment mark. 4 is a sectional view taken along the line -' in FIG. 3, FIG. 5 is a sectional view of a semiconductor device having a wafer alignment mark showing a second embodiment of the present invention, and FIG. 6 is a sectional view of a semiconductor device according to a second embodiment of the present invention. 3 is a manufacturing process diagram showing Example 3. FIG. 11...Mask alignment mark, 12...
...Wafer alignment mark part, 13...Background part, 14...Surroundings, 21, 31, 41...Si
Substrate, 22, 32... Field oxide film, 23,
33... Gate oxide film, 24, 26, 36... Resist film, 25, 34, 45... Opaque film (gate electrode material), 35... Film to be etched, 42...
...first gate oxide film, 43...polysilicon first
Gate film, 44... second gate oxide film.

Claims (1)

[Claims] 1. A method for manufacturing a semiconductor device including a gate forming step of patterning a gate oxide film, comprising: (a) forming a field oxide film in a mark shape on a silicon substrate; (b) forming the field oxide film in a mark shape; (c) forming a resist film and patterning the resist film; (d) using the patterned resist film as a mask, forming a gate oxide film between the field oxide films and the gate; etching the oxide film to remove the patterned resist film, forming an uneven pattern on the field oxide film and the gate oxide film parallel to a scanning line for alignment, and patterning the gate oxide film; , and (e) forming an opaque film in order. 2. Claim 1, wherein the opaque film is made of a gate electrode material, and the gate electrode material is left to be used as an alignment mark after the gate forming step.
A method for manufacturing a semiconductor device having an alignment mark as described in 1. 3. The method of manufacturing a semiconductor device having an alignment mark according to claim 1, wherein a monochromatic light source is used for illumination in the alignment.