JPH0473680A - display control device - Google Patents

Abstract

PURPOSE:To easily and surely catch a specified event and to preferentially display it by preferentially outputting an address which is stored within a prescribed period based on a detection time when an event address is detected. CONSTITUTION:A controller is provided with address storing means 36 and 37, a display data storing means 41, a data transfer means, an event detecting means 50 and an address memory controlling means. And in the case of performing a specified event display, a CPU on the host side of a display device 26 is made to access, for example, the address of font data related to the event in a working area in a VRAM so that it may be detected, and after detecting the address, the address which is stored by the address storing means 36 and 37 is preferentially outputted and the display based on the address is performed. Thus, the specified event to be displayed at a real time is surely caught and rapidly displayed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a display control device, and more specifically, the present invention relates to a display control device, and more specifically, a display that is updated by applying an electric field or the like using, for example, a ferroelectric liquid crystal as an operating medium for updating the display. The present invention relates to a display control device for a display device including a display element that can maintain a state.

[Prior Art] Display devices are generally used in information processing systems as information display means that performs the function of visually expressing information, and the CR7 display device is widely known as such a display device. .

In display control in a CR7 display device, the writing operation of the system CPU to the video memory as a display data buffer on the CRT side and the reading and displaying operation of display data from the video memory by, for example, a CRT controller on the CRT side are independent of each other. is executed.

In the case of CRT display control as described above, the writing of display data to a video memory for changing display information and the operation of reading and displaying display data from the video memory are independent, so the information processing The program on the system side does not need to consider display timing or the like at all, and has the advantage that desired display data can be written at any timing.

On the other hand, however, since a CRT requires a certain length in the thickness direction of the display screen, its overall volume becomes large, making it difficult to downsize the entire display device. Moreover, this impairs the degree of freedom in using an information processing system using such a CRT as a display, ie, the degree of freedom in terms of installation location, portability, etc.

A liquid crystal display (hereinafter referred to as LCD) can be used to compensate for this point. That is, according to the LCD, the entire display device can be made smaller (particularly thinner). Some of these more advanced LCDs include the above-mentioned ferroelectric liquid crystal (FLCFerroelectric liquid crystal).
There is a display device (hereinafter referred to as FLCD: FLC display) using a liquid crystal cell (called UID Crystal), and one of its features is that the liquid crystal cell maintains its display state against the application of an electric field. be. That is, the FLCD has a sufficiently thin liquid crystal cell, and the elongated FLC molecules therein are oriented in a first stable state or a second stable state depending on the direction of applied electric field.
Each orientation state is maintained even when the electric field is removed. Due to such bistability of FLC molecules, FLCD has memory properties.

Details of such FLCs and FLCDs are described in, for example, Japanese Patent Application No. 76357/1983.

As a result, when driving an FLCD, unlike a CRT or other liquid crystal display, there is a time margin in the cycle of continuous refresh drive of the display screen, and there is also a time margin in the cycle of continuous refresh drive of the display screen. , it becomes possible to perform partial rewriting drive that updates the display state of only the changed portion on the display screen.

[Problems to be Solved by the Invention] Therefore, if appropriate and timely partial rewrite driving can be performed in FLCDs, the advantages of FLCDs will be further increased.

In addition, this more flexible F is used as a display device for information processing systems.
The ability to use LCDs interchangeably with CRTs increases the flexibility and value of the system.

From the above viewpoint, it is possible to consider a display control mode in which predetermined partial rewriting is given priority over other partial rewriting of display information. An example of such a display is a display of cursor movement, and the display state of this display must be changed in real time (intuitively) in accordance with the operation of a mouse or the like by the operator.

If such a display is defined as an event, a configuration for performing partial rewriting for the event according to the priority order among multiple events is proposed, for example, in Japanese Patent Application Laid-Open No. 2-934 by the applicant.
It is disclosed in No. 91. However, in display control with this configuration, when a partial rewrite related to an event is performed, the information processing system side provides information for identifying this process to the display device side. Therefore, a control program for an information processing system using such a display device is significantly different from a control program for an information processing system using the above-mentioned CRT as a display device.

As a result, it becomes difficult to configure an information processing system that is compatible with FLCD and CRT.

On the other hand, when using PL(:D) in a display device of an information processing system while being compatible with CRT, an essential problem arises due to its configuration.In other words, the CPU on the system side exclusively handles display data related to display updates. and its address are only transferred to the display device side. Therefore, the problem is how to distinguish the partial rewriting related to the above event from other partial rewriting, and as a result of this discrimination, the partial rewriting related to the event The problem arises as to how to do this on a priority basis.

The present invention has been made in view of the above-mentioned problems, and it is possible to easily and reliably capture a specific event and display it in priority to other partial rewriting displays, and it also provides an information processing system. The purpose of the present invention is to provide an FL (:D) display control device that is compatible with CRT without significantly changing the side software.

[Means for Solving the Problems] To this end, the present invention provides a display control device for a display device that is capable of updating the display state of only the display elements involved in a change in display, in which the address of the display element involved in the change is updated. address storage means for storing display data; display data storage means for storing display data corresponding to each of the display elements;
data transfer means for transferring display data read from the display data storage means to the display device based on an address output from the address storage means; and an address transferred to the display control device when displaying on the display device. an event detection means for detecting a predetermined event address from among the event addresses; and when the event detection means detects the event address, the address stored in the address storage means within a predetermined period based on the detection time is first detected. The present invention is characterized by comprising address memory control means for outputting the address.

[Operation] According to the above configuration, when a predetermined event is displayed, when the CPU on the host side of the display device accesses the address of font data related to the event in the work area in the VRAM, for example, this is detected. After the detection, the address stored in the address storage means is output preferentially and a display is made based on this address.

(The following is a margin) [Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an information processing system using an FLC display device equipped with a display control device according to an embodiment of the present invention as a display device for various kinds of character one-image information.

In the figure, 11 executes control of the entire information processing system (PU), 13 is the main memory that stores the program executed by the CPU II and is used as a work area during this execution, and 14 is the main memory that does not go through the CPU II. A DMA controller (Direct controller) is used to transfer data between the main memory 13 and the various devices that make up this system.
tMemory Access Control
r, hereinafter referred to as DMAC), 15 is a LAN (Local Area Network) such as Ethernet (by XEROX) 16 is a LAN between this system and
Interface, 17 is ROM, SRAM, R32
This is an input/output device (hereinafter referred to as Ilo) having a 32C interface and the like. Various external devices can be connected to l1017. 18 and 19 are a hard disk device and a floppy disk device, respectively, as external storage devices, and 20 is a disk interface for signal connection between the hard disk device 18 and floppy disk device 19 and this system. Reference numeral 21 represents a printer that can be configured with an inkjet printer, a laser beam printer, or the like capable of relatively high-resolution recording, and 22 represents a printer interface for signal connection between the printer and this system. 23 is a keyboard for inputting character information such as various characters, control information, etc., 24 is a mouse as a pointing device, and 25 is a key interface for signal connection between the keyboard 23 and mouse 24 and this system. be. 26 is an FLCD interface 2 as a display control device according to an embodiment of the present invention.
This is an FLC display device (hereinafter also referred to as FLCD) whose display is controlled by 7, and has a display screen using the above-mentioned ferroelectric liquid crystal as its display operation medium. Reference numeral 12 denotes a system bus consisting of a data bus, a control bus, and an address bus for signal connection between the above-mentioned devices.

In the information processing system that connects the various devices described above, the system user generally uses the FLCD26
In other words, the external devices connected to the LAN 16, 11017, the hard disk 18. floppy disk 1
9. Character 2 image information supplied from the scanner 21B, the keyboard 23, the mouse 24, etc., and the main memory 1
3 and related to the user's system operation are displayed on the display screen of the FLCD 26, and the user edits the information and gives instructions to the system while looking at this display. Here, each of the above-mentioned devices etc. is FL
A display information supply means is configured for the CD 26.

FIG. 2 is a block diagram showing details of the FLCD interface 27.

In the figure, 31 is an address bus driver, 32 is a control bus driver, and 33, 43, 44, and 45 are data bus drivers, each of which is connected to each bus of the system bus 12. CPU 1 uses the video RAM (hereinafter referred to as VRAM) on the system side to rewrite display contents, etc.
The absolute address data when accessing
It is applied via the address bus driver 31 to an access monitor circuit 50, which will be described later in FIG. The absolute address input to the access monitor circuit 50 is converted to a display line address, and the F
IFO (A) memory 36 or FIFO (B) memory 3
7 and stored therein. FIFO
(^) 36 and FIFO (B) 37 are FIFOs (First I
n First 0ut) memory, and these FI
The line address data written in the FO(A) 36 and FIFO(B) 37 is selectively read out in response to switching of the second switch S2. The access monitor circuit 50 determines the address data accessed by the CPU II to the memory 41 during a predetermined period, and when a different address is accessed, the data is sent to the sampling counter 3.
4, and the counter 34 counts this. This count value is given to the synchronization control circuit 39 and can be used to determine the ratio of partial rewriting and refresh drive, which will be described later.

The absolute address is also input to the address selector 35 for the CPUIT to access the video memory 41.

These FIFO(A) 36 or FIFO(B) 3
The address data read from 7 and the address data for accessing the video memory 41 from the address counter 38, which will be described later, are selectively selected according to the switching of the third switch S3. is applied to one input section of the address selector 35.

The address counter 38 increments the line address of the video memory 41 by "1" and generates address data for refreshing the entire display screen, and the generation timing of the address data is determined by the synchronization control circuit 39. controlled. This synchronization control circuit 39 also generates switching control signals for the switches Sl, S2, and S3 and a data transfer request signal to a memory controller 40, which will be described later. The timing of the above signal generation by the synchronous control circuit 39 and the switches SL, S2 and S3
The switching timing is controlled in accordance with a horizontal synchronization signal (H3YNC) generated by the FLCD 26 every time one line of the display screen is driven.

A control signal from the CPU II is given to a memory controller 40 via a control bus driver 32, and the memory controller 40 controls an address selector 35 and a video memory 41, which will be described later, in response to this control signal. The memory controller 40 is C
Memory access request signal output from PUII when rewriting data in video memory 41, etc. and synchronization control circuit 39
The output of the address selector 35 is switched in accordance with the arbitration with the data transfer request signal output when displaying the data of the video memo 1J41.
The video memory 41 selects one of the two address data.
give to

The video memory 41 stores display data.
Dual port DRAM (consisting of dynamic RAM, writes and reads display data via data bus driver 33. Video memory 41
The display data written in is read out to the FLCD 26 via the driver receiver 42 and displayed. Further, the driver receiver 42 provides the synchronization signal from the FLCD 26 to the synchronization control circuit 39.

Further, data for setting the ratio of partial rewriting and refresh driving, which will be described later, is provided to the synchronization control circuit 39 via the data bus driver 43.

The FLC panel of the FLCD 26 is provided with a temperature sensor 26a for detecting its temperature.
The output signal of 6a is sent to C via the data bus driver 44.
Transferred to PUII.

In the above configuration, when the CPU II changes the display, the address signal of the video memory 41 corresponding to the desired data rewriting is given to the memory controller 40, and the memory access request signal of the CPU II and the synchronization control circuit 39 are sent to the memory controller 40. Arbitration with the data transfer request signal is performed. Then, when the CPU access side obtains the right, the memory controller 40 instructs the address selector 35 to select the address from the address driver 31 as the address to be given to the video memory 41, that is, the address currently being accessed by the CPU II. conduct. At the same time, a control signal is generated from the memory controller 40 to the video memory 41, and data is read/written via the data bus driver 33.
That is, data in the video memory 41 is rewritten.

At this time, the address data accessed by the CPU II is stored in the FIFO (A) 36 or FIFO (B) 37 via the access monitor circuit 50 and the switch S1, and is used when transferring display data, which will be described later. In this way, the display data access method seen from the CPU II is the same as in the case of the CRT described above.

On the other hand, when data is read from the video memory 41 and transferred to the FLCD 26 for display, a data transfer request is generated from the synchronization control circuit 39 to the memory controller 40, and an address for the video memory 41 is sent to the switch S3. Address counter 3
8 or the FIFO side is selected by the address selector 35 after passing through the address conversion circuit, and a control signal for data transfer is generated from the memory controller 40, so that the shift register is transferred from the memory cell of the video memory 41. The data on the corresponding address line is transferred to the address line and output to the driver 42 in accordance with the control signal of the serial port.

As described above, the synchronization control circuit 39 performs a cycle in which the entire screen is refreshed according to an embodiment of the present invention based on the horizontal synchronization signal H3YNC from the FLCD 26, and a partial rewrite cycle in which the line accessed by cputi is rewritten. Generate the timing that causes Here, the full refresh cycle refers to a cycle in which the lines constituting the display screen are sequentially driven to display one line at a time. is determined. Furthermore, the access line partial rewriting cycle is one in which a line accessed from the CPU II is rewritten within a predetermined time period immediately before the cycle.

In this way, in this example, basically, the operation of refreshing the entire screen of the FLC display 26,
In order to change the display contents, the operation of rewriting the partial line accessed by the CPU II is performed alternately in a time-sharing manner, but the repetition period of these operations and the time ratio of these operations within one cycle are also determined. It can also be set.

With reference to FIG. 3, the basic operation of this example will be described in which the refresh operation and line rewriting operation are performed alternately in a time-sharing manner. Here, the refresh cycle is set to 4 lines, and the access line rewrite cycle is set to 3.
An example is shown in which the line is used as a unit.

In FIG. 3, REE/AC3 is a timing that causes a full refresh cycle and an access line rewrite cycle to occur alternately.When it is "1", it is a full refresh cycle, and when it is "O", it is a timing that causes the access line rewriting cycle to occur alternately. Indicates a rewrite cycle. In addition, T1 represents the full refresh cycle time, and Tb represents the access line rewrite cycle time. In this example,
T, :T, = 4:3, but an optimal value can be selected depending on the required refresh rate, etc.

That is, by increasing the ratio of T, the refresh rate can be increased, and by increasing the ratio of Tb, the responsiveness of partial changes can be improved.

To explain the states of FIFO (A) 3B and FIFO (B) 37, when switch S1 is connected to FIFO (A) 36 side (state A/B of switch S1 = "1"'
), C: The address of the line accessed by PUll is sampled and stored in the FIFO (A) 36. On the other hand, when the switch S1 is connected to the FIFO (B) 37 side (A/B="0"), the line address accessed by the CPU 11 is stored in the PIFO (B) 37. Furthermore, when the switch S2 is connected to the FIFO (A) 36 side (state A/B of switch S2 = "1°'), the FIF
When the address stored in O(A) 36 is output and the switch S2 is connected to the PIFO(B) 37 side, (A/B
="O"), the address stored in the FIFO (B) 37 is output.

One refresh of the entire screen is completed, and the FLCD26
When the address counter 38 outputs the vertical synchronizing signal VSYNC or a carry occurs in the address counter 38, the address counter 38 is cleared and the line output in the next full refresh cycle returns to the 0th line. As described above, the address counter 38 sequentially counts up "1", "2", and "3" in response to the synchronization signal generated each time the synchronization control circuit 39 counts the horizontal synchronization signal H3YNC. This synchronization signal generated by the synchronization control circuit 39 is output in accordance with the parameters M and N input to the synchronization control circuit 39 via the data bus driver 43.

That is, parameters M and N determine the ratio of refresh cycles and partial rewrite cycles in a certain period, and synchronization signals are output for the number of lines in the refresh cycle determined by these parameters, and are not output during partial rewrite.

On the other hand, lines Ll, L2. When the address of L3 is accessed, at this time switch S1 is
If connected to FO(A) 36, Ll, L2.
The address of L3 is stored here, then switch S2
When Ll, L2 .
The address of L3 is output from here, and LL, L2°L3 is selected as the output line. Here, the switching signal of the switch S3 is given to the RFP/8C8 from the synchronization control circuit 39, and in the line access cycle when RFP/AC3 is "1", the FIF is used as the output line address.
O(A).

The output is switched to the FIFO (B) side. REF
When /ACS becomes "1", the switch S3 is switched to the address counter 38 side, and the synchronous control circuit 3 is switched to the address counter 38 side.
The address counter 38 sequentially starts counting up in response to the synchronizing signal output by the address counter 9 in synchronization with the horizontal synchronizing signal H3YNC, and performs the refresh operation from the line following the previous cycle. In FIG. 3, for example, after the line output of L3, "4", "5", "6", which is the continuation of the previous cycle, are displayed.
"," and "7" lines are output.The above operation is repeated in the same way, but the reason why we prepared two FIFOs is to sample the memory accessed address in one, and sample it in the other at the same time. This is to output addresses consistently and efficiently (i.e., the sampling period of the address is
from the start of the output of the access line to the end of the refresh cycle. After the refresh cycle ends, at the same time as the rewriting cycle of the access line that outputs the address sampled in the previous sampling period begins, the address sampling period of the other FIFO starts. It will be started.

As described above, in the basic operation of this example, refresh cycles and line rewrite cycles are alternately repeated, and the third
In the figure, the repetition period is T, with 7 lines as one unit:
Although the explanation has been made assuming that T = 4 = 3, in this example, the environmental conditions such as temperature, the type of data to be displayed, or even F
The ratio between T and T can be changed depending on the refresh rate required depending on the material of the display device of the LCD.

By the way, the above-mentioned partial rewriting makes it possible to update the display state of only the part that corresponds to the change on the display screen, but even in this partial display state update, priority is given to certain actions such as cursor movement. There are some things that should be done. This is because the movement of the cursor needs to be displayed in real time according to the movement of the mouse operated by the operator, whereas, for example, displaying input characters from the keyboard does not necessarily correspond to key operations. It doesn't have to be real time.

Therefore, in one embodiment of the present invention, the access monitor circuit 50 shown in FIG. 2 is used to preferentially perform such predetermined partial rewriting. Hereinafter, preferential partial rewriting will be explained with reference to FIGS. 5 to 9, taking the display of cursor movement as an example.

FIG. 4 is a block diagram showing details of the access monitor circuit 50 shown in FIG. 2, and FIG. 5 is a block diagram showing the details of the access monitor circuit 50 shown in FIG.
A detailed timing chart regarding O(A), FIG. 6 is a flowchart showing the processing procedure by (:PUll) when the cursor is moved, and FIG. Schematic diagram, No. 7
Figure (B) is a schematic diagram showing this VRAM address correspondence, Figures 8 (A) and CB) are schematic diagrams showing cursor mask data and cursor font data, respectively, and Figure 9 is an example of cursor display. FIG.

In FIG. 4, 501 is a comparison circuit which outputs a match signal when the CPU II access address input via the address driver 31 and the event trigger address stored in the first register 46A match. This event trigger address means a predetermined address that the CPU II always accesses when moving the cursor.

502 is an address conversion circuit that converts an absolute address accessed by the CPU II into a line address. That is, the address input to this access monitor circuit via the address bus driver 31 is an absolute address in the VRAM on the system side as shown in FIG. Convert to display line address. Note that the address conversion circuit 47 shown in FIG. 2 is provided for the purpose of returning the converted display line address to an address for accessing the video memory 41.

503 is a comparison circuit which determines whether the access address of the CPU II is for the display area shown in FIG. 7 (A) or (B) or for the work area, and determines whether the access address is for the display area or , outputs an output to that effect.

Here, as shown in FIG. 7(B), the address of the system-side VRAM is, for example, absolute address 0-1.
59, of which 7 addresses in the horizontal direction and 11 lines in the vertical direction are the display area corresponding to the video memory 41 of the FLCD interface 27. That is, the data within this display area will be displayed on the FLCD. On the other hand, as a part other than the display area in VRAM, the address is 7 to 9.17 = 19
．． ..., the right part which is 107 to 109 and address 1
There is a lower portion corresponding to numbers 10 to 159. Of these, the lower part is usually used as a work area for display control.

As is clear from the above, when the CPU II accesses the VRAM on the system side for display control, it accesses not only the display area but also the work area. As a result, the CPU access address input to the access monitor circuit 50 also includes the address of the work area. Therefore, the input address is determined in the comparator circuit 503, and only if this address is in the display area of the VRAM, it is written to the FIFO (A) 36 or FIFO (B) 37, as will be described later. Make it. The configuration of the comparison circuit 503 may be, for example, a comparison circuit that determines whether the upper two digits of the address of the VRAM shown in FIG. 7(B) are 10 or less. In this case, when the upper two digits of the address input to the comparator circuit 503 are 10 or less, it outputs that it is the address of the display area.

Again in FIG. 4, 505 is a latch comparison circuit;
Upon receiving an output from the comparison circuit 503 indicating that the address data is for the display area, the address data is fetched from the address conversion circuit 502 and compared with the previously fetched and latched address data. If this comparison does not match, this newly fetched address data is latched and output to the FIFO memory 36 (37). At the same time, an output indicating that a different line is being accessed is output.

This prevents consecutive accesses to overlapping lines in video memory 41. Note that the above-mentioned output indicating that the access is to a different line is also transferred to the sampling counter 34, and the sampling counter 34 counts this output.

A FIFO control circuit 504 outputs a reset signal in response to a match signal from the comparison circuit 501, and sets the write pointer of the FIFO memory 36 (37) to the beginning of the FIFO memory. As a result, address data to be input into the FIFO memory from now on is stored from the beginning, and is output first when outputting. The FIFO control circuit 504 also outputs data to the FIFO memory 36 (37) in response to the AND between the output from the comparison circuit 503 indicating that it is the display area and the output from the latch comparison circuit 505 indicating that the access is to a different line. Outputs a write signal to this memory,
Writing of address data input via latch circuit 505 is permitted.

The operation of the access monitor circuit 50 described above will be explained with reference to the timing chart of FIFO (A) shown in FIG. When an event of cursor display movement occurs, specifically, when the CPU 1 accesses the address at position A of the cursor font data stored in the work area shown in FIG.
Since this address is stored in A, the comparison circuit 50
1 outputs a match signal. As a result, when the CPU II accesses the address of the display area of VRAM after accessing location A, that address is stored in FIFO (A) 3.
6, and these addresses are first output at the next output timing.

On the other hand, the processing procedure for moving the cursor by CPt1ll at this time will be explained with reference mainly to FIG. 6 and FIG. 7(A).

When the cursor movement process is started, in step S61,
The image at the old position of the cursor, which has been saved in the image storage area of the work area of the VRAM, is written to the specified position in the display area (■ in FIG. 7(A), the same applies hereinafter), and step S
At 62, the image at the new position of the cursor is saved to the image storage area (■ in the figure). Next, in step S63, this saved image and the work area are stored at a predetermined position in FIG.
) with the cursor mask data shown in ) and write it to a predetermined position in the work area (in the figure
). In this image, the part corresponding to "1" of the cursor mask data shown in Figure 8 (A) is the same as the background color and is "O".
The part corresponding to is white. Next, in step S64,
The image synthesized in step S63 is ORed with the cursor font data stored in a predetermined area of the work area and shown in FIG. Then, the image obtained in step S63 is written in the new position of the display area (■ in the figure).
.

The image to be written is one in which a black cursor is displayed within a cursor outlined in white from the background, as shown in FIG. This is because the size of the cursor mask data is made larger than the size of the cursor font data, as shown in FIGS. 8A and 8B.

In the cursor movement process by the CPU II described above, when cursor font data is synthesized in step S64, the CPU II accesses position A of the cursor font data shown in FIG. 7(A). Since this address is stored as an event trigger address in the register shown in FIG. 4, when the CPU II accesses location A, the comparison circuit 501 outputs a match signal, and as described above in FIG. 36 (37)
will be reset. After that, in step S65, the CP
When the UII accesses the display area to write the composite image of the cursor, the address for these writes is FIFO
It will be stored in the memory 36 (37).

By the way, in the system shown in FIG. 1, for example, when executing a predetermined application program,
If this program is stored on an external storage device such as a disk, it must be moved to the system memory. This causes a change in the correspondence between data in the memory and physical addresses (absolute addresses in the above description). In such a case, the absolute address of the cursor font data used as the event trigger address described above also changes, so this is
I have to reset it to 6^.

FIG. 10 is a flowchart showing the processing at this time. That is, when some application program is started, the operation of this program is performed in step 5IOI. At this time, a bus error in this operation is always checked in step 5103. In step 5103, for example, if the started program is not in the system memory, a bus error occurs, and then in step 5104
Then, it is determined whether this bus error was caused by the absence of a program in the memory, and if the determination is negative, it is determined that there is an abnormality in the system and the process proceeds to the bus error processing routine of step 5ilo. If it is determined that the application program is not in memory, step 510
In step 5, it is determined whether there is enough free space in the system memory to transfer this application program stored in an external storage device such as a disk. If it is determined that there is not enough free space, move the low-priority program to the disk in step S63, and if there is enough free space, proceed directly to step 5107, where the application program is moved from the disk. Transfer to system memory. Next, in step 5108, mapping in memory is performed. This determines the correspondence between virtual addresses in the memory of the entire system and physical addresses on the memory. Based on this, in step 5109,
A new absolute address of position A of the cursor font data is set in register 46A.

In the embodiment described above, the address data of the line to be partially rewritten is stored in the FIFO memory, but in this configuration, when the CPIJ accesses a predetermined event trigger address, the address data stored in the FIFO memory is stored in the FIFO memory. will not be output. On the other hand, as an address data storage medium, for example, SRAM
By using , after outputting the address for preferential partial rewriting, it is also possible to output previously stored address data and rewrite this portion.

FIG. 11 is a block diagram showing the configuration of the FLCD interface in such a case. In Figure 11, 1
45 and 146 are SRAM (Al and SR
AM(B), 147 is writing in SRAM145.146.

This is an address controller that controls the read address. 60 is the access monitor circuit 5 shown in FIG.
Access monitor circuit 14 having almost the same configuration as 0
Reference numeral 8 denotes an SRAM control circuit, which controls the timing of address data output by the address controller 147 in accordance with the control signal from the access monitor circuit 60 and the switch S from the synchronization control circuit 39, as will be described later. , that is, controls the timing of data writing and reading in the SRAMs 145 and 146.

FIG. 12 is a block diagram showing detailed configurations of access monitor circuit 60 and address controller 147.

The access monitor circuit 60 includes a comparison circuit 601. Address conversion circuit 602. Comparison circuit 603 and latch comparison circuit 6
05, and each of these circuits performs the same operation as each circuit shown in FIG. The SRAM control circuit 148 outputs an event occurrence signal in response to the match signal from the comparison circuit 601, and also outputs the display area address from the comparison circuit 603 and accesses a different line from the latch comparison circuit 605. A write signal is output when there is an output indicating that , and a read signal is output in synchronization with the signal S3 from the synchronization control circuit 39. Also, SRAM145.146
outputs a sampling period signal that manages the sampling period to the

In the address controller 147, 1471 is an address control circuit, and the above-mentioned SRA MllJ control circuit 1
48, the SRAM address counter 1474 and register 1472 are controlled. S.R.A.
M address counter 1474 is SRAMI45 (1
46), each time address data is written to the SRAM
This is a counter that counts up every time address data is read from 145 (146), and this count-up is performed by an enable signal from the address control circuit 1471.
At the end of sampling (address data writing) to M145 (146), the count value of each counter 1474 is stored.

1473 is a comparison circuit that compares the count value at the end of sampling stored in the register 1472 and the counter 147.
When the contents of 4 match, an output to that effect is output to the address control circuit 1471.

The operation of the address controller 147 described above will be explained with reference to FIG. 13.

When writing (sampling) to the SRAM 145 (146), at the start, the address control circuit 1471 outputs a clear signal to set the address (count value) of the address counter 1474 to "O" (■ in FIG. 13).

Thereafter, the address control circuit 1471 outputs an enable signal for each write signal from the SRAM control circuit 148 and sequentially counts up the count value of the address counter 1474. When an event occurrence signal is output, the address control circuit 1471 outputs an enable signal and sequentially increments the count value of the address counter 1474. Address counter 14 at this time
740 count value is stored (■ in the figure). After that, similarly output an enable signal in response to the above write signal,
The count value of address counter 1474 is counted up. After the above event occurrence signal is output, SRA
Address counter 147 in M145 (146)
The address data stored at the address indicated by the count value of 4 is, for example, data indicating the movement of the cursor, as shown in the above embodiment. When the above operation is repeated and the sampling period ends, the address control circuit 1471 stores the count value of the address counter 1474 at that time in the register 1472, and also uses the count value at the time of event occurrence stored in the register 1472 as an address. This is the count value of the counter 1474 (■ in the figure).

At the time of reading following the above-mentioned sampling period, the address control circuit 1471 outputs an enable signal for each read signal from the SRAM control circuit 148, and the address counter 1
474 count value is increased to 0 or more As explained above, since reading starts from the address at the time the event occurred (■ in the figure), partial rewriting display such as cursor movement is performed with priority. become. after that,
Similarly, an enable signal is output for each read signal to increment the count value, and when this count value matches the count value at the end of sampling stored in the register 1472 (■ in the figure), the address control circuit 147
1 outputs a clear signal, sets the count value of the address counter 147 to "0", and reads out the address data previously stored in the SRAM 145 (146) (in the figure)
).

In each of the above-mentioned embodiments, the display for preferentially performing partial rewriting,
In other words, although we showed an example of cursor movement as an event,
It goes without saying that this is not an example of an event. Hereinafter, in the system shown in FIG. 1, a series of processes performed by the user operating the keyboard 23 and mouse 24 while looking at the display on the FLCD 26 will be taken as an example. Display shows some of the events with reference to an example. In addition, in the explanation of the display related to the event, "(event)
”.

FIG. 14(A) This is the initial screen, and shows a state where nothing is being done after the power is turned on.

Figure 14 (B) Double-click the cabinet icon with the mouse (1 in the figure).

This causes the cabinet window to open (event) and the window showing the disk area to close (event).

FIG. 14(C) Click on one of the binders in the cabinet with the mouse (2 in the figure).

This causes the clicked binder to be inverted (
event).

Figure 14 (D) Open a certain document file (3 in the figure).

Figure 14 (E) Specify a range and move the cursor vertically using the mouse or arrow keys. As a result, the portion of the text specified in the range is inverted in black and white (4 in the figure) (event).

Figure 14 (F) On the screen shown in Figure 14 (E), click on the bottom left corner of the screen that says "Heading Form" (5 in the figure) or press the corresponding function key F1.
Press. As a result, the menu screen at the bottom of the screen changes (6 in the figure) (event).

Figure 14 (G) Shows the state in which other document files are opened.

FIG. 14(H) Click the print portion at the top of the document window shown in FIG. 14(G) with the mouse (7 in the same figure).

This causes a subwindow for printing to be displayed (event).

FIG. 14 (1) An error occurs when printing is instructed with the mouse, and an error message is displayed (event).

(The following is a blank space) [Effects of the Invention] As is clear from the above description, according to the present invention, when displaying a predetermined event, the CP on the post side of the display device
For example, when U accesses the address of the font data related to the above event in the work area in VRAM, this is detected, and after the detection, the address stored in the address storage means is output preferentially and a display based on this address is performed. It will be done.

As a result, specific events to be displayed in real time can be reliably captured and displayed promptly. Further, it is possible to CR the FLCD equipped with the display control device of the present invention without significantly changing the software on the information processing system side.
It can be made compatible with T.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an information processing system incorporating a display control device according to an embodiment of the present invention, and FIG. 2 is an FL as a display control device shown in FIG.
FIG. 3 is a block diagram showing the configuration of the CD interface; FIG. 3 is a timing chart for explaining the basic operation of the FLCD interface shown in FIG. 2; FIG. 4 is a detailed diagram of the access monitor circuit shown in FIG. A block diagram showing the configuration; FIG. 5 is a timing chart for explaining the operation of the FLCD interface shown in FIG. 2 according to an embodiment of the present invention; FIG. 6 is a cursor according to an embodiment of the present invention. Flowchart showing the processing procedure for movement; FIG. 7(A) is a conceptual diagram of the system-side VRAM to explain the above-mentioned cursor movement; FIG. 7(B) shows the address correspondence between the display area and work area in the above-mentioned VRAM. A conceptual diagram of the VRAM for explanation; FIGS. 8(A) and (B) are conceptual diagrams of cursor mask data and cursor font data for the cursor movement, respectively; FIG. 9 is a conceptual diagram of the cursor mask data and cursor font data for the cursor movement FIG. 10 is a flowchart when a predetermined application program is executed to explain setting of an event trigger address to a register according to an embodiment of the present invention, and FIG. 11 is a schematic diagram showing a display example of the present invention. A block diagram showing the configuration of an FLCD interface according to another embodiment. FIG. 12 is an access monitor circuit shown in FIG. 11. FIG. 13 is a block diagram showing the detailed configuration of the SRAM control circuit and address controller; FIG. 13 is a conceptual diagram of the SRAM for explaining the operation of the FLCD interface according to another embodiment of the present invention; FIGS. (1) is an FLC for illustrating some examples of event triggers according to embodiments of the present invention.
It is a front view which shows the example of a display of D. 11...cpu. 12... Address bus, 13... Main memory, 14... DMA controller, 15... LAN interface, 16... LAN. 17... I10 device, 18... Hard disk device, 19... Floppy disk device, 20... Disk interface, 21... Printer, 22... Printer interface, 23... Keyboard, 24. ...Mouse, 25...Key interface, 26...FLCD (FLCD display), 26
a... Temperature sensor, 27... FLCD interface, 31... Address bus driver, 32... Control bus driver, 33, 43.4
4.45...Data bus driver, 34...Sampling counter, 35...Address selector, 36...FIFO (A) memory, 37...FIFO (B) memory, 38...Address counter , 39... Synchronous control circuit, 40... Memory controller, 41... Video memory, 42... Driver receiver, Sl, S2. S3...Switch, 46A, 46B...Register, 47...Address conversion circuit, 50, 60...Access monitor circuit, 145...S
RAM (A), 146... SRAM CB), 147... Address controller, 14g... SRAM control circuit, 5 (11,601... Comparison circuit, 502, 602... Address conversion circuit, 503 , 60
3... Comparison circuit, 504... FIFO control circuit, 505, 605... Latch comparison circuit, 1471...
Address control circuit, 1472...Register, 1473...Comparison circuit, 1474...SRAM address counter. Figure Figure (A) Cursor 7f Take L1) β1 L2>, /2 Figure Figure 13 Procedure Transfer Device (Method) October 17, 1990

Claims (1)

[Scope of Claims] 1) A display control device for a display device capable of updating the display state of only a display element related to a display change, comprising: address storage means for storing an address of a display element related to the change; display data storage means for storing display data corresponding to each of the display elements; and display data read from the display data storage means based on an address output from the address storage means and transferred to the display device. data transfer means; event detection means for detecting a predetermined event address from among the addresses transferred to the display control device when displaying on the display device; and when the event detection means detects the event address, detecting the event address; A display control device comprising: address memory control means for first outputting the address stored in the address storage means within a predetermined period based on a time point. 2) The display control device according to claim 1, wherein the event address is an address of a font used to display the event.