JPH0474350U - - Google Patents
Info
- Publication number
- JPH0474350U JPH0474350U JP11875090U JP11875090U JPH0474350U JP H0474350 U JPH0474350 U JP H0474350U JP 11875090 U JP11875090 U JP 11875090U JP 11875090 U JP11875090 U JP 11875090U JP H0474350 U JPH0474350 U JP H0474350U
- Authority
- JP
- Japan
- Prior art keywords
- bits
- data
- memory section
- bit generator
- memory device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 2
- 238000013500 data storage Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Detection And Correction Of Errors (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Description
図は本考案の一実施例を示す構成ブロツク図で
ある。
１……メモリ部、１１……データ格納領域、１
２……パリテイチエツクビツト格納領域、２……
誤り検出・訂正回路（ＥＤＣ回路）、３……チエ
ツクビツトジエネレータ、４……ラツチ手段、５
１，５２……第１、第２マルチプレクサ、６１〜
６３……バツフア、７……内部制御回路。
The figure is a block diagram showing an embodiment of the present invention. 1...Memory section, 11...Data storage area, 1
2... Parity check bit storage area, 2...
error detection/correction circuit (EDC circuit), 3... check bit generator, 4... latch means, 5
1, 52...first, second multiplexer, 61~
63...Batsuhua, 7...Internal control circuit.
Claims (1)
ＥＣＣ化構成のメモリ部と、メモリ部から読み出
されたデータとパリテイチエツクビツトとを入力
し、誤りを検出し可能であればそれを訂正する誤
り検出・訂正回路と、前記メモリ部にデータを書
き込むときにチエツクビツトを発生させるチエツ
クビツトジエネレータとを備えたメモリ装置であ
つて、 前記メモリ部から読み出されるデータを保持す
るラツチ手段と、 このラツチ手段が保持しているデータの上位側
ｎビツトと書込みデータの上位側ｎビツトとを切
換える第１のマルチプレクサと、 前記ラツチ手段が保持しているデータの下位側
ｍビツト（ｎ，ｍは任意の整数）と書込みデータ
の下位側ｍビツトとを切換える第２のマルチプレ
クサと、 第１、第２のマルチプレクサによつて選択され
た合わせてｎ＋ｍビツトのデータを前記メモリ部
と前記チエツクビツトジエネレータとに与える回
路と を設けたことを特徴とするメモリ装置。[Claims for Utility Model Registration] A memory section with an ECC configuration that stores data and parity check bits, and a system that can detect errors by inputting the data and parity check bits read from the memory section. A memory device comprising an error detection/correction circuit for correcting errors, if any, and a check bit generator for generating check bits when writing data to the memory section, the memory device holding data read from the memory section. a first multiplexer for switching between the upper n bits of the data held by the latch means and the upper n bits of the write data; n, m are arbitrary integers) and the lower m bits of the write data, and a total of n+m bits of data selected by the first and second multiplexers are transferred to the memory section and the lower m bits of the write data. A memory device comprising: a check bit generator; and a circuit for supplying a check bit generator.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11875090U JPH0474350U (en) | 1990-11-13 | 1990-11-13 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11875090U JPH0474350U (en) | 1990-11-13 | 1990-11-13 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0474350U true JPH0474350U (en) | 1992-06-29 |
Family
ID=31866704
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11875090U Pending JPH0474350U (en) | 1990-11-13 | 1990-11-13 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0474350U (en) |
-
1990
- 1990-11-13 JP JP11875090U patent/JPH0474350U/ja active Pending
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