JPH0571977B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a storage device used in a data processing device, and particularly to error correction thereof.

(Prior Art) Conventionally, as shown in FIG. 3, this type of storage device is configured to read and write data by accepting read and full write/partial write operation requests from an arithmetic processing unit. Was. In FIG. 3, 50 is a write data register, 51 is an address register, 52 is a main control circuit, 53 is a selection circuit, 54 is an ECC check bit generation circuit,
55 and 56 are the first and second banks, respectively;
57 is a read data register, and 58 is an ECC check correction circuit.

In the storage device shown in FIG. 3, an ECC check bit generation circuit and an ECC check bit correction circuit 58 are used.
Further, a pair of banks 55 and 56 are provided, and each bank 55 and 56 can be independently interleaved and read/written. For example, if you request a partial write operation to the first bank 55 and then request a full write operation or a partial write operation to the second bank 16, the ECC
In the check bit generation circuit 54, the first bank 5
The write operation of the second bank 56 is prohibited because a certain amount of time is occupied for the operation of the second bank 56.

(Problems to be Solved by the Invention) Therefore, the storage device according to the above-mentioned prior art has a drawback in that a write operation cannot be performed for a certain period of time after a partial write operation.

An object of the present invention is to provide a plurality of banks for independently performing read and full write/partial write operations, to check and correct read data, and to provide an ECC check bit generation circuit for all write operations and for partial write operations. It is an object of the present invention to provide a memory device which eliminates the above-mentioned drawbacks by individually providing ECC check bit generation circuits, and is configured so that a full write operation can be performed immediately after a partial write operation.

(Means for Solving the Problems) A storage device according to the present invention includes a plurality of banks,
ECC check correction circuit, first and second
It is equipped with an ECC check bit generation circuit, and is configured to enable full writing even immediately after partial writing when performing full write operations and partial write operations to different banks.

Data can be independently read from each of the plurality of banks, and full/partial writing can be performed on the banks.

The ECC check and correction circuit is for checking and correcting data read from the bank.

The first ECC check bit generation circuit generates ECC check bits for all writes, and the second ECC check bit generation circuit generates ECC check bits for all writes.
The ECC check bit generation circuit is for partial writing.
This is for generating ECC check bits.

(Example) Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of a storage device according to the present invention. In FIG. 1, 5 is a write data register, 6 is an address register, and 7 is a write data register.
1 is a main control circuit, 9 is a selection circuit, 11 and 12 are first and second ECC check bit generation circuits, 16 and 17 are first and second banks, respectively, 19 is a read data register, and 21 is a
This is an ECC check correction circuit.

Signals are transferred from an arithmetic processing unit (not shown) via a write data signal line 1, an address signal line 2, and a control signal line 3, and are sent to a write data register 5, an address register 6, and a main controller, respectively. The signal is received by the circuit 7.

FIG. 2 is a timing chart showing the operation of the storage device shown in FIG. The storage device shown in FIG. 1 operates in synchronization with the clock 100 shown in FIG. Control signal 101 on signal line 3 and write data 103 on signal line 1 are received by the storage device at the timing of clock #0. Partial writing of the first bank 16 is executed according to the received command. Address signals on signal line 15 are supplied to first bank 16 . The main control circuit 7 controls each circuit and reads data from the memory cell array of the first bank 16. The main control circuit 7 sets the read data to the read data register 19 via the signal line 18 at the timing of clock #2, and the output is set to the ECC via the signal line 20.
It is added to the check correction circuit 21 and ECC check is performed.

If there is an error in the data, the ECC check and correction circuit 21 also corrects the error bit. Therefore, the corrected read data is sent to the arithmetic processing unit (not shown) via the signal line 4 and is also provided to the selection circuit 9. The selection circuit 9 selects the write data on the signal line 8 and the read data on the signal line 4 according to the partial write signal, and
The above composite write data is applied to the second ECC check bit generation circuit 12. The second check bit generation circuit 12 clocks the ECC check bit #3 for the composite write data on the signal line 10.
occurs on the signal line 13 due to the timing of the first
The data is sent to the memory cell array of bank 16 for writing.

Timing 11 at clock #2 timing
The control signal of 0 and the write data at timing 111 are transferred to the second bank 17 . When a full write operation is required, all write data on signal line 8 is sent to the first ECC check bit generation circuit 11 for all write data, and the ECC check bit on signal line 14 is sent to the first ECC check bit generation circuit 11 for all write data. 112 occurs.

Furthermore, the above data is sent to the second bank 17 at timing 113 of clock #4. Second
A write operation to bank 17 of
It is clear that this can be done simultaneously with the partial write operation to 6.

(Effects of the Invention) As explained above, the present invention performs a full write operation immediately after a partial write operation by providing an ECC check bit generation circuit for each of the full write operation and the partial write operation. Therefore, interleaving can be easily performed and writing performance can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram partially showing one embodiment of a storage device according to the present invention. Figure 2 shows the first
3 is a timing chart showing the timing relationship of the storage device shown in the figure. FIG. 3 is a block diagram partially showing an example of a storage device according to the prior art. 5, 50...Write data register, 6, 51...
Address register, 7, 52... Main control circuit, 9,
53... Selection circuit, 11, 12, 54... ECC check bit generation circuit, 16, 17, 55, 56...
Bank, 19, 57...Read data register, 2
1,58...ECC check correction circuit, 1 to 4,8,
10, 13 to 15, 18, 20...Signal line, 100
~113...Timing.

Claims (1)

[Scope of Claims] 1. A plurality of banks from which data can be read independently and from which full/partial writing can be performed, and an ECC for checking and correcting data read from the banks. It is equipped with a check correction circuit, a first ECC check bit generation circuit for generating ECC check bits for full write, and a second ECC check bit generation circuit for generating ECC check bits for partial write. 1. A storage device characterized in that when an operation and a partial write operation are performed on different banks, the entire write can be performed immediately after the partial write.