JPH0476479B2 - - Google Patents

Description

[Detailed Description of the Invention] <<Industrial Application Field>> The present invention relates to an interface circuit for a liquid crystal display device, and in particular, utilizes the interface signal of a CRT display device, which is often used in personal computers, etc. It is designed to be able to replace a conventional liquid crystal display device.

<<Summary of the Invention>> The present invention utilizes interface signals of a CRT display to create timing signals necessary for driving a liquid crystal display.
The aim is to provide a large flat display terminal that can replace CRT display terminals.

<<Prior art>> Liquid crystal display devices have the characteristics of being thin, low voltage, and low power consumption, and have recently been put into practical use as display terminals for personal computers, word processors, etc. using large dot matrix panels. It is being done. However, the number of display dots on a CRT display is 640×200 dots or 640×
In order to display 400 dots, simple matrix driving required the screen to be divided into an upper half and a lower half at 1/100 duty and 1/200 duty. This inevitably causes a decrease in contrast as the duty ratio decreases, so a countermeasure is taken by multiple matrix driving. However, when driving multiplexed matrices in this way, the interface circuit is equipped with a data storage circuit for the upper half and a data storage circuit for the lower half, and writes are performed sequentially for each address, while reading is performed for the upper half. There are problems in that the circuit configuration is complicated and the cost is high, as the lower half of the memory circuit is read out at the same time. Therefore, it is difficult for those who are adopting a liquid crystal display device for the first time to understand and use it as an interface.

<<Problems to be Solved by the Invention>> As mentioned above, the interface circuits of conventional liquid crystal display devices had the disadvantages of complex circuit configurations and high costs. Research and development of active matrix panels has progressed and reached a level where sufficiently high contrast can be obtained even at 1/400 duty. The present invention provides an interface circuit suitable for such a high-duty drive liquid crystal display device and attempts to overcome the conventional drawbacks.

<<Example>> Next, a specific example of the present invention will be described. The figure is a circuit diagram showing one embodiment of the present invention. In the figure, the X-ray display control circuit 1 uses a horizontal synchronization signal
A circuit that inputs Hsyc, sets a delay time, and adjusts the timing with display data. Y-axis display control circuit 2
is a circuit that inputs the vertical synchronization signal Vsyc and sets a delay time from this signal to determine the timing with the display data. The variable dot counter 3 is a circuit that counts the clock signal CK to count the number of horizontal dot clocks. The 4-bit shift register 5 is a circuit that converts the serially input video signal VD into a parallel signal. 1/4 counter 4
is a circuit that generates a latch signal for latching the display data of the 4-bit shift register 5. It is composed of the above circuit.

Next, the operation will be explained. horizontal sync signal,
Hsyc is input to the monostable multivibrator 9 of the X-axis display control circuit 1. The output of the monostable multivibrator 9 falls to "0" after a delay time determined by the time constants of the capacitor 14 and the variable resistor 15. Furthermore, since the flip-flop circuit 10 has been reset, the output of the NOR circuit 12 rises to "1". The Y-axis display control circuit 2 also has a similar configuration, and outputs "1" to the AND circuit 17 with a delay after inputting the vertical synchronization signal Vsyc. Therefore, after the outputs of the X-axis display control circuit 1 and the Y-axis display control circuit 2 match "1", the AND circuit 17
Outputs clock signal CK. Variable dot counter 3 counts this clock signal CK. Set the count value of variable counter 3 to 640
When set to , the carry signal CL ₁ is generated by the 640th clock signal. This carry signal CL ₁ is input to the flip-flop circuit 10. Therefore, the output of the flip-flop circuit 10 becomes "1", so the AND circuit 17 stops outputting the clock signal CK. On the other hand, the video signal
VD shifts and shifts the output of the AND circuit 17.
The signal is input to a 4-bit shift register 5 which serves as a clock. Therefore, each time the clock signal is input, data is shifted in and taken in.
The 1/4 counter 4 is a frequency dividing circuit that receives the clock signal from the AND circuit 17, and generates a carry signal _CL2 at the fourth clock signal. This carry signal _CL2 latches the data in the 4-bit shift register 5. The latched 4-bit video data _D0 to _D3 are 4-bit
Output from the shift register. The 1/4 counter 4 carry signal _CL2 is delayed by the D-type flip-flop circuit 8 and outputted as a shift clock signal SC to the data shift register of the liquid crystal driving circuit.

The carry signal _CL1 of the variable dot counter 3 is delayed by the D-type flip-flop circuit 6 to generate an output LD as a latch signal for one line of the liquid crystal drive circuit.

When the vertical synchronizing signal Vsyc is input, it is the data of the first row of scanning lines. Since the signal is input to the NOR circuit 22, the output of the NOR circuit 21 is set to "1". The latch signal LD of the liquid crystal drive signal is
The signal is delayed by a half cycle of the clock signal CK by the D-type flip-flop circuit 7 and input to the NOR circuit 21, so that the output of the NOR circuit 21 is reset to "0". The output signal of this NOR circuit 21
The FRM is output to the liquid crystal drive circuit as scanning start data (frame signal) on the common side of the liquid crystal drive circuit. Further, the output FRM of the NOR circuit 21 is the same as that of the flip-flop circuit 11.
The polarity of the liquid crystal drive voltage is inverted every frame, and an AC drive control signal M for AC drive is output.

<<Effects of the Invention>> As described above, according to the present invention, CRT
Using the display interface signals,
The circuit configuration is extremely simple and the cost is low.
An interface circuit for a liquid crystal display device compatible with a CRT display can be configured. Also,
The present invention has great advantages, such as the fact that the same liquid crystal drive circuit as conventional ones can be used.

[Brief explanation of the drawing]

The figure is a diagram showing an embodiment of the present invention. 1...X-axis display control circuit, 2...Y-axis display control circuit, 3...Variable counter, 4...4-bit shift register, 6, 7, 8...D-type flip-flop circuit, 11...Flip-flop circuit.

Claims (1)

[Claims] 1. An X-axis display control circuit for setting the display timing of a horizontal synchronization signal in an interface circuit of a liquid crystal display device incorporating a drive circuit for driving a liquid crystal panel having an X-Y matrix structure. a Y-axis display control circuit for setting the display timing of the vertical synchronization signal; and a clock generation circuit that generates a dot lock signal when the display timings of the X-axis display control circuit and the Y-axis display control circuit match. a latch signal generation circuit for counting the clock signal of the clock generation circuit and generating a latch signal for display data of one horizontal axis; converting the serial display data into a parallel signal and sequentially transmitting the display data to the drive circuit; an S/P conversion circuit for outputting a signal, and a transfer clock generation circuit for generating a transfer clock for frequency-dividing the dot clock signal of the clock generation circuit and transferring the output of the S/P conversion circuit to the drive circuit. a frame signal generation circuit for generating a drive timing signal for the first scanning line of the liquid crystal panel based on the vertical synchronization signal; and a frame signal generation circuit for frequency-dividing the output signal of the frame signal generation circuit to drive the liquid crystal panel in an alternating current manner. 1. An interface circuit for a liquid crystal display device, comprising an alternating current drive signal generation circuit for generating a signal for the purpose of generating an AC drive signal.