JPH0476920A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To flatten a surface enough and to prevent increases in contact resistance with efficient deposits of SOG in a side recess of the first wiring by spin coating with SOG after an SiO2 side spacer is provided on a side face of the first wiring. CONSTITUTION:An SiO2 film formed on a first aluminum wiring 2 is etched back. As a result, an SiO2 film remains on a side face of the wiring 2 and is used as a side spacer 3-1. Thus, the top face of the wiring is exposed, while the side face is coated with the spacer 3-1. Next, SOG(Spin-On-Glass) is applied by a spin coater. In this case, the side face of the wiring 2 is coated with the SiO2 spacer 3-1 which is well-wettable with SOG, and the top face of the wiring shows an exposure of aluminum which is poorer-wettable with SOG than SiO2. Therefore, SOG penetrates deeply into a recess on the side of the wiring 2 so as to flatten enough and prevent increases in contact resistance.

Description

[Detailed description of the invention]

[Industrial Field of Application] The present invention relates to a method of manufacturing a semiconductor device having two or more layers of wiring. [Prior Art] As semiconductor devices become more highly integrated, the wiring within them becomes interlayer! ! It has come to be made up of multiple layers with the membrane sandwiched in between. Note that aluminum is mainly used as the material for the wiring. FIG. 3 shows the above semiconductor device manufactured by a conventional method. In FIG. 3, 1 is a semiconductor substrate, 2 is a first aluminum wiring, 3 is a 5i02 film, and 4 is an SOC film (
Spin-On-Glass), 4-1 is the inner wall exposed part,
5 is a SiO2 film, 6 is a second aluminum wiring, 7 is a VI
A hole 8 is a contact portion. A silicon substrate is used as the semiconductor substrate 1, on which a first aluminum wiring 2 is formed, and a 5iOz film 3 as an interlayer insulating film is formed thereon. sOG film 4. A SiO□ film 5 is sequentially formed. After the VIA hole 7 is opened by etching, the second aluminum wiring 6
is formed and contacts the first aluminum wiring wA2 at the contact portion 8. Thereby, the first aluminum wiring 2 and the second aluminum wiring 6 are electrically connected. The interlayer insulating film is for insulating between the first aluminum wiring 2 and the second aluminum wiring 6 in a portion other than the VIA hole 7. Note that the same applies to contact holes. The only difference is that the contact hole connects to the drain or source of the transistor rather than the wiring. The SOG film 4 is used as a flattening material to make the surface, which will be the base upon which the second aluminum wiring 6 is formed, as uneven as possible. This is because if there are large irregularities on the surface of the base, there is a risk that the second aluminum wiring 6 will be disconnected or short-circuited. Since the SoG film 4 tends to contain moisture in the air and become a chemically unstable substance, the 5in2 film 5 is applied thereon to prevent this.

[Problem to be solved by the invention]

(Problems) However, the semiconductor devices manufactured by the conventional method described above have the following problems. The first problem is that flattening by the SOG film 4 is not sufficient, and the wiring is likely to be disconnected or short-circuited. The second problem is that the contact resistance of the contact portion 8 is large. (Description of Problems) First, the first problem will be explained. The surface to which SOG is applied is S10. This is the surface of the membrane 3. In other words, the wettability of SOG is the same in all parts, and even though the wettability is the same, SOG has a viscosity like water, so when using a spin cord, it tends to accumulate in the recesses, and it tends to accumulate in the recesses compared to the convex parts. The thicker the coating, the thicker the coating. Therefore, although it is alleviated, unevenness inevitably remains,
Flattening is not performed sufficiently. If wiring is applied to a surface with uneven surfaces, there is a greater possibility of wire breakage or short circuits. ■ Next, the second problem will be explained. In FIG. 3, prior to applying the second aluminum wiring 6, V
The IA hole 7 is opened, which allows the SOG film 4 to
It will be exposed at the inner wall exposed portion 4-1. From this part, the solvent, moisture, etc. contained in the SOG film 4 come out as gas (outgas). Since the formation of the second aluminum wiring 6 is performed in the presence of gases such as those described above, the surface of the aluminum undergoes reactions such as oxidation with these gases and changes in quality. Contact part 8
The aluminum part also undergoes such deterioration, resulting in an increase in electrical resistance compared to pure aluminum. As a result, contact resistance becomes large. An object of the present invention is to solve the above-mentioned problems.

[Means to solve the problem]

In order to solve the above-mentioned problems, the present invention provides a method for manufacturing a semiconductor device in which a second wiring is formed above a first wiring.
+ 02gI formation, a step of forming side spacers on the side surfaces of the first wiring by etch-hacking the siO□ film, a step of forming an SOC film by spin coating, and a step of forming the 1sOG film. The method includes a step of etching and hacking until the upper surface of the first wiring is exposed, and then a step of forming a SiO□ film by vapor phase growth.

[For production]

If SOG is spin-coated after side spacers made of Si are provided on the sides of the first wiring, SiO□ has good wettability to SOG, so SOC can be efficiently attached to the recesses on the sides of the first wiring. This makes it possible to flatten the surface well. Also, since the SOC film is etched until the top surface of the first wiring is exposed and then the 5i02 film is formed on top of it, when the VIA hole is opened to connect to the second wiring, 5 Oct on the inner wall! * is never exposed. Therefore, gas that would alter the surface of the wiring material is not released, and an increase in contact resistance is prevented.

【Example】

Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a diagram illustrating a method for manufacturing a semiconductor device according to the present invention. The symbols correspond to those in Figure 3, 3-1
4-2 is the side spacer, and 4-2 is the initial surface. Since manufacturing is performed in the order shown in FIGS. 1(a) to 1(e), the description will be made in this order. (1) Step of FIG. 1(a) A first aluminum wiring 2 is formed on the semiconductor substrate 1. The M thickness is, for example, about 8000 people. (2) Step of FIG. 1 <a) After the first aluminum wiring 2 is formed, a SiO film 3 is formed by plasma vapor deposition. For example, when formed under the following conditions, the film The total number of people is approximately 4,000. Temperature...300°C RF specific output -100W (RF:Radio Fr
pressure ・=7.2Torr SiH4 gas・=100 sccm (standard
d cc /sin) N, O gas -4500sec
(3) The film 3 in step 5102 of FIG.
Etching). As a result, a SiO□ film remains on the side surface of the first aluminum wiring 2,
This will be referred to as side spacer 3-1. Thus, the top surface of the first aluminum wiring 2 is exposed, and the side surfaces are covered with the side spacers 3-1. Note that the etching conditions at this time are, for example, as follows. RF specific output: 350 W CF, gas -20 sccm H2 gas -125 ccn Pressure: 1.3 Pascals (4) Step (d) in Figure 1 Next, SOG is applied using a spin coater. Although the wettability is the same, since it has a viscosity like water, it tends to accumulate in the recesses when spin-coding, and the coating is thicker on the recesses than on the convex parts. However, in the present invention, the side surface of the first aluminum wiring 2 is covered with a side spacer 3-1 made of Sin, which has good wettability to SOG. On the other hand, on the upper surface of the first aluminum wiring 2, aluminum, which has poor wettability with SuG compared to SiO□, is exposed. Due to such a difference in wettability, the SOG easily enters the recesses on the sides of the first aluminum wiring 2, and planarization is performed satisfactorily. The surface of the initial SOG film 4 thus obtained is located at the initial surface 4-2 indicated by the dotted line. The surface of the SOG film 4 is lowered by light etching using the RrE method until the upper surface of the first aluminum wiring 2 is exposed. The illustrated SOG film 4 shows the state at this time. (5) The SiO2 film 5 is formed by the process shown in FIG. 1(e) by plasma vapor phase epitaxy. This is carried out under the following conditions, for example, and the film thickness of S is 1 μm.
If! A film 5 can be formed. Temperature...300°C RF specific output...100 W Pressure -1,2 Torr Si H4 gas -100 sec N20 gas -4500 sec By going through the above process, the unevenness of the surface has been further flattened between the eyebrows. An insulating film is formed. On the other hand, a via hole is opened using conventional techniques, and then a second aluminum wiring is applied. Since the interlayer insulating film is sufficiently planarized, the second aluminum wiring is less likely to be disconnected or short-circuited. FIG. 2 shows a semiconductor device manufactured by such a method of the present invention. The symbols correspond to those in FIGS. 1 and 3. In the case manufactured up to the stage shown in FIG. 1 (E), only the Sl○2 film 5 exists above the first aluminum wiring 2, so when the VIA hole 7 is opened, it is exposed as its inner wall. The material is only SiO2. Unlike SOG, SiO□ does not emit gas that would react with aluminum and cause it to change in quality. Therefore, when the second aluminum wiring 6 is applied, the contact resistance of the contact portion 8 does not increase. Although the case where the aluminum wiring has two layers has been described above, it is of course applicable to the case where the aluminum wiring has three or more layers. Furthermore, although the SiOz film is formed by plasma vapor deposition, it is assumed that aluminum, which is expected to cause hillocks, is used as the wiring material. Materials with less hillock formation (e.g. Al-5i)
-Cu alloy), other vapor phase growth methods may be used.

【Effect of the invention】

As described above, the method for manufacturing a semiconductor device of the present invention provides the following effects. (2) Good planarization by the SOG film. In the present invention, we focused on the fact that the wettability of SiO□ to SOG is better than that of the wiring material (aluminum) to SOG, and after providing a site spacer made of SiO□ on the side surface of the first wiring, we spin SOG. Coat. By doing so, SOG can be efficiently attached to the recesses on the sides of the first wiring, and the surface can be smoothly planarized. Therefore, the second wiring formed on the flattened surface is less likely to be disconnected or short-circuited. ■ Contact resistance between wires does not increase. In the present invention, the SOG film is etched back until the upper surface of the first wiring is exposed, and then the SiO□ film is formed thereon. As a result, S exists above the first wiring.
Only the i0g film is present (conventionally, a SOG film layer also existed). In this state, when a VIA hole for connection with the second wiring is opened, the SOG film is not exposed on the inner wall of the VIA hole. Therefore, gases that alter the surface of the wiring material are not released, and an increase in contact resistance is prevented.

[Brief explanation of the drawing]

FIG. 1: A diagram illustrating the method of manufacturing a semiconductor device according to the present invention. FIG. 2: Third diagram of a semiconductor device manufactured by the method of the present invention.
Figure: In a diagram of a semiconductor device manufactured by a conventional method, I is a semiconductor substrate, 2 is a first aluminum wiring, 3 is S
iO□ film, 3-1 is side spacer, 4 is SOG film, 4
-1 is the inner wall exposed part, 42 is the initial surface, 5 is the S+Oz film,
6 is a second aluminum wiring, 7 is a VIA hole, and 8 is a contact portion. Patent applicant Fuji Xerox Co., Ltd. Representative Patent Attorney Tomio Honjo Figure 1

Claims (1)

[Claims] A method of manufacturing a semiconductor device in which a second wiring is formed above a first wiring includes a step of forming an SiO_2 film by vapor phase growth after forming the first wiring;
a step of forming a side spacer on the side surface of the first wiring by etching back two films, a step of forming a SOG film by spin coating, and a step of exposing the top surface of the first wiring with the SOG film. 1. A method for manufacturing a semiconductor device, comprising the steps of: etching back the substrate, and then forming a SiO_2 film by vapor phase growth.