JPH0645313A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain an layer insulating film having a constant thickness in the chemical-mechanical polishing method. CONSTITUTION:An oxide film 25 is grown under normal temperature on a semiconductor substrate 21 on which a wiring pattern is already formed, a plasma nitride film 24 is then grown and a plasma oxide film 26 is moreover grown thereon. Next, when the entire part is etched back by a chemical- mechanical polishing method, a nitride film on the wiring acts as a stopper of etching, the oxide film on the non-wiring area is no more etched and the stepped portion between the wiring part and non-wiring part can be eliminated, providing a flat layer insulating film. Thereby, the thickness of the layer insulating film is uniformed by using a nitride film as the etching stopper. Moreover, since a thick insulating film can be formed on the wiring during the polishing process, any stress is not applied to the wiring and reliability can also be improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device in which an interlayer film is planarized by using a chemical-mechanical polishing method.

[0002]

2. Description of the Related Art In the conventional flattening technique of an interlayer insulating film, first, as shown in FIG. 3A, a silicon oxide film 32 having a film thickness of 0.2 μm is formed on a semiconductor substrate 31, and a film thickness of 0. 5
A wiring material 33 having a thickness of μm is exposed, and a desired wiring pattern is formed by using a normal photolithography technique and an etching technique. Next, a film thickness of 0.
An oxide film 36 (hereinafter abbreviated as a plasma oxide film) having a thickness of 4 μm or less is grown (FIG. 3B), a coating insulating film 37 is applied to a thickness of 0.1 μm (FIG. 3C), and the film thickness is further increased. 0.4μ
The plasma oxide film 38 of m was grown to flatten the interlayer insulating film (FIG. 3D).

However, although this method enables local planarization, it cannot eliminate the absolute step difference between the wiring portion and the non-wiring portion, and cannot maintain a constant height. Further, since the coating insulating film is used, there is a problem in reliability that moisture from the coating insulating film corrodes the wiring.

In order to solve such a problem, a chemical-mechanical polishing method (Semiconductor Technology Symposium Proceeding (ME.
Thomas et al. , "Mechanical
Planarization Process Ch
aractation ”, Semi.Tec
h. Symp. Proc. , Pp296-299 (19
91). ) And Proceedings VLSI Multilevel Interconnect Conference (P. Ren
teln et al. , "Characteriza
tion of Mechanical Planari
zation Process ”, Proc, VMIC
91, pp 57-63 (1991). )) Has been widely studied and is about to be applied to production.

In this technique, for example, as shown in FIG. 4A, first, a silicon oxide film 42 is formed on a semiconductor substrate 41, a wiring material 43 having a film thickness of 0.5 μm is deposited, and a normal photo film is formed. A desired wiring pattern is formed by using the lithography technique and the etching technique. Next, atmospheric pressure CVD
A silicon oxide film 45 (hereinafter referred to as atmospheric pressure oxide film) having a film thickness of 2 μm is grown by the method (FIG. 4B), and the entire surface is etched back by 1.2 μm in the film thickness direction by the chemical-mechanical polishing method. By doing so, the interlayer insulating film is flattened (FIG. 4C),
An interlayer film is formed.

[0006]

In this method of manufacturing a semiconductor device using the chemical-mechanical polishing method, etching is performed for a fixed time, so that if the etching rate varies, the etching amount changes. However, there is a problem that the thickness of the interlayer film after etching changes. Thereby, for example, when the film thickness of the interlayer insulating film becomes thick, when the wiring material of the upper layer is deposited after forming the through hole, the through hole becomes too deep, and thus the wiring material cannot be deposited. Come out. On the other hand, if the film thickness is too thin, the wiring will be exposed, causing a problem of short-circuiting with the wiring in the upper layer, or due to the stress generated during polishing,
There is a reliability problem that the wiring is damaged.

[0007]

According to a method of manufacturing a semiconductor device of the present invention, an insulating film is formed on a semiconductor substrate on which an element is formed, and a chemical-mechanical polishing method is used to etch back to flatten the surface of the semiconductor device. In the manufacturing method according to item 1, the insulating film is composed of at least two layers, and at least one layer other than the uppermost layer is an insulating film having a slower etching rate by a chemical-mechanical polishing method than a film above it, which is a chemical- It acts as a stopper for etch back by mechanical polishing.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described with reference to the drawings. FIG. 1 is a process sectional view showing a first embodiment of the present invention.

First, as shown in FIG. 1A, a silicon oxide film 12 is formed on a semiconductor substrate 11 to have a film thickness of 0.5 μm.
m wiring material 13 is deposited, and a desired wiring pattern is formed by using ordinary photolithography technology and etching technology. Next, the nitride film 14 formed by the plasma CVD method
(Hereinafter, abbreviated as plasma nitride film) is grown to a film thickness of 0.2 μm (FIG. 1B), and a normal pressure oxide film 15 having a film thickness of 1.1 μm is grown thereon (FIG. 1C). Next, the etch rate of the oxide film is set to 0.1 μm / m using a chemical-mechanical polishing method.
In, when the etching rate of the nitride film is 0.02 μm / min, the entire surface is etched back for 13 minutes. When the film thickness of the nitride film on the wiring is about 0.16 μm, the etching is finished. The oxide film on the non-wiring is not etched any more, the step between the wiring portion and the non-wiring portion is eliminated, and the insulating film can be flattened (FIG. 1D). Further, a plasma oxide film 16 having a thickness of 0.8 μm is grown to form an interlayer film (FIG. (E)).

As described above, when the nitride film on the wiring is exposed by the chemical-mechanical polishing method, the etch rate of the chemical-mechanical polishing method on the entire surface including the oxide film on the non-wiring is equal to the etch rate of the nitride film. Therefore, the total etching amount does not change so much, and the film thickness of the interlayer insulating film becomes constant.

Next, a second embodiment of the present invention will be described with reference to FIG.

First, as shown in FIG. 2A, a silicon oxide film 22 is formed on a semiconductor substrate 21, a wiring material 23 having a film thickness of 0.5 μm is deposited, and ordinary photolithography and etching techniques are used. Then, a desired wiring pattern is formed. Next, an atmospheric pressure oxide film 25 having a film thickness of 0.8 μm is grown (FIG. 2B), and a plasma nitride film 24 having a film thickness of 0.2 μm is grown thereon (FIG. 2C). A plasma oxide film 26 having a thickness of 0.9 μm is grown (FIG. 2 (d)). next,
When the entire surface is etched back for 11 minutes using the chemical-mechanical polishing method under the same conditions as in the first embodiment, the thickness of the interlayer film on the wiring is about 0.96 μm for the reason described above.
At the point where m is reached, the etching is completed and the interlayer film can be flattened (FIG. 2 (e)). As a result, not only is the thickness of the interlayer insulating film constant, but the insulating film on the wiring can be kept thick during polishing, so that the interlayer insulating film can be flattened without applying stress to the wiring.

[0013]

As described above, according to the present invention, an insulating film having a slow etching rate in the chemical-mechanical polishing method is placed in the interlayer insulating film other than the uppermost layer so that the insulating film can be formed by the chemical-mechanical polishing method. Since it can be used as a stopper for etch back, the film thickness of the interlayer insulating film becomes constant. As a result, the interlayer film thickness on each part of the semiconductor substrate does not change so much. When the wiring material of the upper layer is deposited after forming the through hole, the wiring material cannot be deposited because the through hole becomes too deep. There is no problem or problem that the wiring is exposed and short-circuited with the wiring in the upper layer.

Further, by laying one or more insulating films under the stopper film, it is possible not only to prevent accidents in which the wiring material is exposed by the etch back by the chemical-mechanical polishing method, but also Since the insulating film on the wiring can be kept thick during polishing, stress can be applied to the wiring, and there is no problem in reliability.

[Brief description of drawings]

FIG. 1 is a sectional view showing a first embodiment of the present invention in process order.

FIG. 2 is a sectional view showing a second embodiment of the present invention in the order of steps.

FIG. 3 is a process sectional view showing a conventional technique.

FIG. 4 is a process sectional view showing another conventional technique.

[Explanation of symbols]

 11, 21, 31, 41 Semiconductor substrate 12, 22, 32, 42 Silicon oxide film 13, 23, 33, 43 Wiring material 14, 24 Plasma nitride film 15, 25, 45 Normal pressure oxide film 16, 26, 36 Plasma oxidation Film 37 Coating insulating film 38 Plasma oxide film

Claims (2)

[Claims] 1. A method of manufacturing a semiconductor device, wherein an insulating film is formed on a semiconductor substrate on which an element is formed and the surface is flattened by etching back by a chemical-mechanical polishing method, wherein the insulating film comprises at least two layers, At least one layer other than the uppermost layer is an insulating film having a slower etch rate in the chemical-mechanical polishing method than the upper layer film, and is used as an etch-back stopper by the chemical-mechanical polishing method. Of manufacturing a semiconductor device. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the insulating film having a slow etching rate is a silicon nitride film.