JPH0478049B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to an operation switching circuit suitable for use when selecting an arbitrary operation mode from among a plurality of operation modes in various electronic devices to perform a desired circuit operation. .

[Background technology]

In recent years, many electronic devices have multiple functions; for example, record players have a rotation speed of 45 rpm,
It is common to have two types of rotation speeds, 331/3 rotations, and television receivers also have PAL,
A device that can be used in common with SECAM and NTSC systems has been developed.

In such cases, it is desirable to be able to arbitrarily select a desired operation in a simple manner. Therefore, the inventors of the present application conducted various technical studies on the above-mentioned operation switching circuit on the premise that it would be implemented as a semiconductor integrated circuit, and as a result, the circuit configuration was simple, the number of circuit elements was small, and the external connection terminal It has been found that it is desirable to be able to reduce the number of devices, consume less power, and have high input impedance.

By the way, "Integrated Circuit Handbook" (June 1981)
Published by Asakura Shoten Co., Ltd., p. 222) has multiple voltage comparators, and applies reference voltages with different voltage levels to one input terminal of each voltage comparator, and applies reference voltages of different voltage levels to the other input terminal. Applying an analog signal in common to
A circuit technique is described that can obtain a digitized output voltage from the voltage comparator.
According to the above circuit technology, the switching operation as described above can be performed based on the output voltage, but the plurality of voltage comparators are constantly energized, so power consumption is large.

[Purpose of the invention]

An object of the present invention is to utilize a parallel A/D converter to switch the operation mode of a controlled system according to the signal level of an analog signal supplied as a control signal. An object of the present invention is to provide a circuit technology configured to reduce power consumption.

The above and other objects and novel features of the present invention will become apparent from the present specification and the accompanying drawings.

[Summary of the invention]

A brief summary of the invention disclosed in this application is as follows.

That is, the first conductivity type semiconductor control element, e.g.
A first A/D converter is composed of an NPN transistor, etc., and compares a first reference voltage with a control signal, and a second conductivity type semiconductor control element, for example, a PNP transistor, is composed of a second reference voltage. A second A/D converter that compares the voltage with the control signal is provided to achieve the object of the present invention, which is to reduce power consumption by the first and second A/D converters. It is.

〔Example〕

Next, an embodiment of an operation switching circuit to which the present invention is applied will be described with reference to FIGS. 1 and 2.

The feature of this embodiment is that the voltage level of the control signal Vc supplied from one input terminal _T1 and the reference voltage
The present invention is configured to obtain a logical output voltage in which the combination of binary levels changes depending on the three values by comparison with V ₁ and V ₂ .

The circuit block shown in Figure 1 compares the control signal V _C with the reference voltages V ₁ and V ₂ and determines the output voltage.
This is to obtain V _A and V _B , and the circuit block is 2
The code converter and circuit block that obtain three outputs from the input are controlled systems, and in this example, the chroma signal C
NTSC demodulation circuit 100, PAL demodulation circuit 101,
The signal is configured to be selectively supplied to the SECAM demodulation circuit 102.

Transistors Q ₁ and Q ₂ constitute a first A/D converter as referred to in the present invention, and transistors Q ₃ and Q ₄ constitute a second A/D converter as referred to in the present invention. In this case, Q1 and Q2 and Q3 and Q4 each form a differential pair and constitute a differential amplifier that performs a comparison operation. Resistor R5 connects transistor differential pair Q3-Q4
By connecting one side Q4 of the second AD
Obtain the converter output voltage VB. Transistor Q ₅ ,
Q ₆ constitutes a current mirror circuit, and together with resistor R ₆ , it has the same potential as the above output voltage VB (GND level)
The output voltage VA is obtained by using the reference potential as the reference potential. Further, resistors R ₂ , R ₃ , and R ₄ are voltage dividing circuits, and apply reference voltages V ₁ and V ₂ to the respective bases of transistors Q ₂ and Q ₄ .

By the way, the voltage level of the control signal V _C is
As shown in Figure A, the level changes in three stages: L, M, and H, and the H level is equal to the reference voltage _V1 , and the M level is equal to the reference voltage _V2 . Now, if the control signal V _C is at L level as shown between t ₁ and t ₂ , transistors Q ₁ and Q ₄ are turned off, and transistors Q ₅ and Q ₂ , resistor R ₁ , and transistor Q _{3 are} turned off. A current path is formed. But resistance
Since R ₁ is provided, the amount of current flowing through this current path is reduced. Then, the collector voltage V ₀ of the transistor Q ₂ decreases in level (V _BEQ5 ) as shown in FIG. 2B, and the output current I ₀ and the resistor R ₆
The output voltage V _A becomes high level as shown in FIG. 2C due to the voltage drop between the two.

On the other hand, since transistor Q ₄ is in the off state,
The output voltage V _B becomes low level (GND level) as shown in FIG. 2D. Therefore, when the control signal V _C is low level, the output voltage V _A is high level,
Output voltage V _B becomes low level.

As shown between t ₂ and _{t 3} , when the control signal V _C is at M level, transistors Q ₁ and Q ₃ are turned off and transistor Q ₄ is turned on. Therefore, the output current I ₀ is obtained in the same manner as above, and the output voltage V _B also becomes high level due to the current flowing through the resistor R ₅ . That is, in this case, both output voltages V _A and V _B become high level.

As shown between t ₃ and _{t 4} , when the control signal V _C is at H level, the transistor Q ₁ is turned on and the transistors Q ₂ and Q ₃ are turned off. Above voltage V ₀
increases to almost + _Vcc , and no output current _I0 can be obtained. Therefore, the output voltage V _A drops to low level (GND level).

On the other hand, since a current path of transistor Q ₁ , resistor R ₁ , transistor Q ₄ , and resistor R ₅ is formed, the output voltage V _B remains at a high level. Therefore, in this case, the output voltage V _A becomes a low level and the output voltage V _B becomes a high level, contrary to the above-mentioned t ₁ to _{t 2} .

That is, by changing the level of the control signal V _C to the three values L, M, and H, the combination of the output voltages V _A and V _B changes to the three values.

The code converter is composed of a combination of phase inverters 1, 2 and AND circuits 3, 4, 5.
Between _t1 and _t2 , a low level input signal is supplied to the AND circuit 3, so the output signal becomes low level. Also, since high level and low level input signals are supplied to the AND circuit 4,
Its output signal also becomes low level. However, since a high level input signal is simultaneously supplied to the AND circuit 5, the output signal of the AND circuit 5 becomes high level.

As a result of the above circuit operation, MOSFETQ ₁₁ and Q ₁₂ provided as switching elements are both turned off, and MOSFETQ ₁₃ is turned on. Then, the chroma signal C is sent to the SECAM demodulation circuit 10.
2, and the television receiver receives SECAM format broadcasts.

Next, the circuit operation between _t2 and _t3 will be described. Since the output voltages V _A and V _B are both high level, the output signal of the AND circuit 4 becomes high level. However, high level input signals are not supplied to AND circuits 3 and 5 by phase inverters 1 and 2, respectively, and the output signals of AND circuits 3 and 5 become low level.

Therefore, in this case, the MOSFET Q ₁₂ operates in the on state, the chroma signal C is supplied to the PAL demodulation circuit 102, and the television receiver receives PAL broadcasting.

Furthermore, regarding the circuit operation between t ₃ and t ₄ ,
The phase of the output voltage V _A is inverted by the phase inverter 1, and both high level input signals are supplied to the AND circuit 3. Therefore, the output signal of AND circuit 3 becomes high level, and the output signals of AND circuits 4 and 5 both become low level. Therefore, the MOSFET Q ₁₁ operates in the on state, the chroma signal C is supplied to the NTSC demodulation circuit 100, and the television receiver receives the NTSC broadcast.

That is, according to this embodiment, one input terminal
By changing the level of the control signal V _C supplied to T ₁ in three stages, a television receiver capable of commonly receiving NTSC, PAL, and SECAM format broadcasts can be adapted to receive each format. I can do it. Moreover, all of transistors Q ₁ to _{Q 4} are not always energized, and the load resistance is
Current flows through R ₅ and R ₆ at the same time because the control signal V _C
This is only when the is M level, and it is also possible to reduce power consumption.

〔effect〕

(1) All of the transistors Q ₁ to _{Q 4} constituting the first and second A/D converters do not operate at the same time, and the current flows through the first and second A/D converters. Since the current is reduced by the resistor R ₁ and the output current I ₀ is also cut off according to the level of the control signal V _C , the effect of reducing power consumption can be obtained.

(2) Due to (1) above, it is suitable for portable electronic devices that use batteries as a power source.

(3) Since the number of circuit elements is small and the circuit configuration is simple, it is easy to integrate into a semiconductor integrated circuit.

(4) Since both the first and second A/D converters are configured with differential amplifiers, they can have high input impedance, even if the control signal V _C has a small level difference. Operation switching can be performed with high sensitivity.

Although the invention made by the present inventor has been specifically explained based on the examples above, the present invention is not limited to the above examples, and it is understood that various changes can be made without departing from the gist of the invention. Needless to say.

For example, NPN transistors Q ₁ and Q ₂ may be replaced with N-channel MOSFETs, and PNP transistors Q ₃ to Q ₆ may be replaced with P-channel MOSFETs. Furthermore, the reference voltages V ₁ and V ₂ may be obtained using a constant voltage circuit.

[Application field]

In the above description, the invention made by the present inventor has mainly been described with respect to switching of the reception mode of a television receiver, which is the background application field of the invention, but the invention is not limited thereto.

For example, it can be used to change the rotational speed of a turntable in a record player, or to change the tape speed in a VTR or tape recorder.

The present invention can be used at least for semiconductor integrated circuits for electronic devices that require mode switching.

[Brief explanation of drawings]

FIG. 1 shows a circuit diagram showing an embodiment of an operation switching circuit to which the present invention is applied, and FIGS. 2A to 2D show waveform diagrams for explaining the circuit operation. ...Operation switching circuit, ...Code converter,
...Controlled system, V _C ...Control signal, V ₀ , V _A , V _B
... Output voltage, V ₁ , V ₂ ... Reference voltage, Q ₁ , Q ₂ ,
Q ₃ , Q ₄ , Q ₅ , Q ₆ ...transistor, R ₁ , R ₂ ,
R ₃ , R ₄ , R ₅ , R ₆ ... Resistor, 1, 2 ... Phase inverter, 3, 4, 5 ... AND circuit, Q ₁₁ , Q ₁₂ , Q ₁₃
...MOSFET, 100, 101, 102... demodulation circuit.

Claims (1)

[Claims] 1. A pair of NPN differential transistors and a pair of PNP differential transistors are connected to a first power supply terminal and a second power supply such that their common emitter terminals are connected to each other via a common current regulating means. terminals, and the base terminal of one transistor of each differential transistor pair is connected to the base terminal of each differential transistor pair, which is connected in series between the first and second power supply terminals. Reference voltages of different levels are applied respectively, and a common signal is supplied to the base terminal of the other transistor of each differential transistor pair, and a common signal is supplied from the collector terminal of one of the transistors of each differential transistor pair. An operation switching circuit characterized in that it is configured to generate an operation switching control signal by supplying a signal based on each extracted voltage to a decoder and decoding it. 2. The operation switching circuit according to claim 1, wherein the current regulating means is a resistive element.