JPH0834024B2 - Screen display enable signal generation circuit for video equipment - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a screen display permission signal generating circuit for a video device, and more specifically, a video tape recorder for displaying a screen by a quick start from a power "ON". Below VT
R), the improvement of the phase lock state detection circuit that can detect the phase lock state of video movies etc. at an early stage.

[Prior Art] In video equipment such as VTRs and video movies, the motor control circuit of the cylinder motor or capstan motor controls the phase in order to control the rotation of the cylinder (or drum, hereinafter cylinder) and the tape running speed as desired. PLL control is performed by two feedback loops of speed control and speed control.

And to display the image on the screen with the video device,
This is because the control system for these cylinder motors and capstan motors has become stable and the head can scan the tracks in the correct phase.

[Problems to be solved] Control system for cylinder motor and capstan motor is PLL
Since it is controlled, the time when the phase relationship between the head and track due to the rotation of each motor becomes the phase locked state is
It has been almost constant since the power was turned on. Conventionally, the screen display permission signal was generated at a fixed timing from the time the power was turned on in time with this phase lock state, and a stable image was displayed on the screen. it's shown. However, when an image is displayed at such a timing, it takes time until the image is displayed, and a viewer who sees the image may be annoyed, so that an earlier display is desired.

Therefore, it is conceivable to detect the phase lock state early and display the screen immediately, but in reality, the phase lock state may be entered or released in the initial stage of entering the phase lock. It is not enough to detect the phase locked state, and there is the problem that stable image display is difficult.

SUMMARY OF THE INVENTION The present invention is to solve the above-mentioned problems of the prior art, and an object of the present invention is to provide a screen display permission signal generation circuit of a video device capable of performing a quick start of the screen display from the power "ON". And

[Means for Solving the Problems] In the configuration of the screen display permission signal generation circuit of the video equipment of the present invention which achieves such an object, the first phase lock detection signal is sent from the cylinder motor phase control system at a predetermined cycle. It receives and stores it as bit information, and receives a second phase lock detection signal from the capstan motor phase control system at a predetermined cycle and shifts the bit information in accordance with the first shift register. And the bit information of the first and second phase lock detection signals is stored in each stage of the first and second shift registers. A detection circuit for detection and a storage circuit for storing a detection signal from the detection circuit and generating a screen display permission signal in response to the detection signal are provided.

[Operation] As described above, a shift register is provided corresponding to each of the cylinder motor control system and the capstan motor control system, and the phase lock detection signal is stored as a flag bit in each shift register at a predetermined cycle. , The screen display permission signal is generated when the storage bits of all the shift registers indicate the phase lock detection signal generation state, so it is necessary to take sufficient timing until image permission as in the past. In addition, there is no unstable image display as when simply detecting the phase lock state, and the phase lock detection signal is detected multiple times in succession. It can be performed.

[Embodiment] An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment when the screen display permission signal generating circuit of the video equipment of the present invention is applied to a VTR, and FIG. 2 is a timing chart for explaining the operation.

In FIG. 1, reference numeral 1 denotes a VTR screen display permission signal generation circuit, which is a phase counter 3 built in a phase control circuit 2 of a cylinder motor control system (hereinafter, cylinder control system) to a trapezoidal wave section pulse 23 ( (See Fig. 2 (d)) and sample pulse from the sample pulse generation circuit 4 of the cylinder control system.
22 (see FIG. 2 (c)). Further, the trapezoidal wave section pulse 23a (see FIG. 2 (d)) and the sample pulse of the capstan control system are generated from the phase counter 6 built in the phase control circuit 5 of the capstan motor control system (hereinafter, capstan control system). Sample pulse 22a from circuit 7 (second
(See FIG. 3C)).

Since the screen display permission signal generation circuit 1 periodically receives signals having a corresponding relationship from the cylinder control system and the capstan control system, the signal of the cylinder control system will be mainly described here. Signals corresponding to those of the stun control system are indicated by adding "a" after the same number, and the description thereof is omitted.

The phase counter 3 is, for example, a 10-bit counter, receives the reference phase signal 20 serving as the phase reference shown in FIG. 2 (a), and starts counting at its rising edge. The count state of this value is shown as an analog voltage value in FIG. 6B, which is from zero volt to the power supply voltage V.
The trapezoidal waveform 21 has a ramp voltage characteristic that linearly increases the value up to CC. Phase counter 6 for capstan control system
Similarly, the waveform is shown in parentheses as 21a (b).
Are shown together with.

The trapezoidal wave section pulse 23, 23a shown in FIG. 2 (d) is the count value of the phase counters 3, 6 whose pulse width indicates the phase locked state with respect to this trapezoidal waveform 21 (21a) as shown by the dotted line. The pulse width is set to match the range. The pulse width may span the entire trapezoidal slope.

The sample pulse generation circuit 4 uses a speed pulse (FGm
Pulse) and its phase pulse (PGm pulse)
A pulse that is synchronized with the pulse, is in phase with the PGm pulse, and has the same period as the trapezoidal wave section pulse 23 is generated as a sample pulse. Here, this pulse is generated in response to the signal from the VFF generating circuit 8 which generates a pulse signal having a cycle (30 Hz) twice that of the vertical synchronizing signal, in synchronization with its rising timing. The sample pulse generated in this manner is the sample pulse 22 shown in FIG. 2 (c).

The sample pulse generation circuit 7 is also a velocity pulse (FG
c pulse) and its phase pulse (PGc pulse) to receive a similar pulse from the control signal generation circuit 9 corresponding to the VFF generation circuit 8 and rise to the second pulse of 30 Hz.
A sample pulse 22a as shown in FIG.

These sample pulses 22 and 22a and trapezoidal section pulse 23 and 2
The image display permission signal generation circuit 1 that receives 3a is a four-stage configuration (4) that receives the phase lock detection circuit 10 of the cylinder control system, the phase lock detection circuit 11 of the capstan control system, and the phase lock detection signals from them. Bit) shift registers 13 and 14, AND circuits 15a, 15b and 15c, NOR circuit 16a, NOR circuit 16b, OR circuit 16c, and flip-flop (F / F) 17, and the screen is displayed on the flip-flop 17. Generate a display permission signal.

The phase lock detection circuits 10 and 11 are respectively configured by AND gates, and the outputs thereof are input to the first stages of the shift registers 13 and 14, respectively. This circuit uses sample pulse 22 (22
Fig. 2 (e) shows that the sample 23 (23a) is generated when the trapezoidal wave section pulse 23 (23a) is detected by a) and the trapezoidal wave section pulse 23 (23a) is at the high level (hereinafter "H"). The lock detection signal 24 (24a) shown is generated.

The shift registers 13 and 14 have the lock detection signals 24 and 24 described above.
When a occurs, the output of "H" is received from the phase lock detection circuits 10 and 11 at the first stage and "1" is stored as bit information. When the lock detection signals 24 and 24a are not generated, the low level (hereinafter "L") output is received and the bit information of "0" is stored in the first stage of each shift register 13 and 14. The information of "1" and "0" stored in the first stage is sequentially shifted to the next stage every time the sample pulses 23 and 23a are generated.

As a result, when the phase lock state is almost completely achieved, a lock detection signal is generated at every generation of each sample pulse 23, 23a, and the shift registers 13, 14 '
All bits stored in each stage of the stage become "1".

The output of each stage of the shift register 13 of the cylinder motor control system is input to the AND circuit 15a, and the output of each stage of the shift register 14 of the capstan motor control system is input to the AND circuit 15b. When all the bits of each stage of 14 become "1", the AND circuit 15c receiving the outputs of the AND circuits 15a and 15b generates the output of "H". In other words,
Both the cylinder control system and the capstan control system enter the phase lock state, which is 4 of shift registers 13 and 14.
It is detected by the AND circuits 15a, 15b, 15c that the phase locked state is entered while the memory information of the stages continues to the extent of being set to "1".

This means that, since each shift register 13 and 14 has a four-stage configuration here, the phase lock detection period continues for four sample pulse cycles. This state occurs when the phase lock state becomes almost stable after the phase lock state is entered. Hello shift register
Before the storage bits of 13,14 are all "1", when the phase lock is not detected even once by the sample signal 23,23a in either the cylinder control system or the capstan control system, in other words, it is a little unstable and locks. When the detection state does not continue for four cycles of the sampling period and is released even once, the phase lock state detection signal is not generated at the output of the AND circuit 15c.

The phase lock state detection signal generated in the AND circuit 15c is applied to the D terminal of the flip-flop 17 and stored in the flip-flop 17. And flip-flop 17
Is output from the output terminal 18 as a screen display permission signal. As a result, once the phase lock state detection signal is generated, even if one value of each stage of the shift registers 13 and 14 changes to "0" due to noise or the like, it does not affect the detection of the phase lock state. The screen display permission signal continues to be generated.
This enables stable image display.

Here, the storage data of the flip-flop 17 indicating that both the cylinder control system and the capstan control system have entered the phase locked state are reset by the NOR circuits 16a, 16b and the OR circuit 16c. The NOR circuits 16a and 16b receive the outputs of the respective stages of the shift registers 13 and 14, and the OR circuit 16c outputs the NOR
It receives the outputs of circuits 16a and 16b. Therefore, all bits stored in each stage of the shift register of either the cylinder motor control system or the capstan motor control system are "0".
At this time, a reset signal is generated from the OR circuit 16c. As a result, the data of the flip-flop 17 is reset either in the initial state at the time of power “ON” or in the control system of either the cylinder motor control system or the capstan motor control system for a relatively long time. It is when the phase locked state is released. In such a case, a distorted image cannot be obtained even when the screen is displayed, so that the screen display permission signal should be released.

As described above, by using the four-stage shift register, the phase locked state is fixed to some extent, and the screen display permission signal can be immediately generated in a stable state. Moreover, this screen display permission signal is at a point near immediately after both the cylinder control system and the capstan control system enter the phase lock state and become stable, so it is sufficient to stabilize each as in the conventional case. It is possible to generate a screen display permission signal in a short time and immediately display an image without securing time.

As described above, in the embodiment, the shift register 1
Although the number of stages of 3,14 is a four-stage configuration, this can be determined according to the characteristics of the phase control circuit of the video equipment, and multiple stages of shift registers are used for both the cylinder control system and the capstan control system. It should be provided.

In the embodiment, the sample pulse for sampling the trapezoidal wave section pulse is generated from the signal of the predetermined frequency which is synchronized with the FG pulse and is aligned with the phase of the PG. The phase matches the pulse,
Moreover, the pulse may have the same cycle as the phase counter or a cycle of an integral multiple thereof. Further, the present invention is not limited to the phase lock detection by such a sample pulse, and the phase lock signals can be obtained in a predetermined cycle from the respective phase control circuits of the cylinder motor control system and the capstan motor control system. You may use it. In such a case, it suffices to receive the phase lock signal at a predetermined cycle, and the number of stages of the shift register is determined by the relationship with the cycle in which the phase lock signal is obtained. It suffices to generate a state detection signal.

[Effects of the Invention] As can be understood from the above description, in the present invention, shift registers are provided corresponding to the cylinder motor control system and the capstan motor control system, and the phase lock detection is performed in each shift register. The signal is stored as a flag bit in a predetermined cycle, and the screen display permission signal is generated when the storage bits of all shift registers indicate the phase lock detection signal generation state. The screen display can be performed immediately after entering a substantially stable phase lock state in which a signal is continuously detected a plurality of times.

As a result, it is possible to realize a video device that can display the screen with a quick start at the same time when the power is turned on.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment when the screen display permission signal generating circuit of the video equipment of the present invention is applied to a VTR,
FIG. 2 is a timing chart for explaining the operation. 1 ... Screen display permission signal generation circuit, 2 ... Cylinder control system phase control circuit, 3,6 ... Phase counter, 3a, 7a ... Trapezoidal section pulse, 4 ... Cylinder control system sample pulse generation circuit , 4a, 7a …… Sample pulse, 5 …… Capstan control system phase control circuit.

Claims (1)

[Claims] 1. A first shift register that receives a first phase lock detection signal from a cylinder motor phase control system at a predetermined cycle, stores it as bit information, and shifts corresponding to the cycle, and a capstan. A second shift register that receives a second phase lock detection signal from the motor phase control system at a predetermined cycle, stores it as bit information, and shifts in accordance with the cycle, and first and second shift registers. A detection circuit for detecting that the bit information of the first and second phase lock detection signals is stored in each stage, and a detection signal from the detection circuit, and screen display permission according to the detection signal. A screen display permission signal generation circuit for a video device, comprising: a storage circuit that generates a signal.