JPH0478827U - - Google Patents
Info
- Publication number
- JPH0478827U JPH0478827U JP12344590U JP12344590U JPH0478827U JP H0478827 U JPH0478827 U JP H0478827U JP 12344590 U JP12344590 U JP 12344590U JP 12344590 U JP12344590 U JP 12344590U JP H0478827 U JPH0478827 U JP H0478827U
- Authority
- JP
- Japan
- Prior art keywords
- current
- voltage
- phase comparator
- converts
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 8
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Description
第１図はこの考案の一実施例であるＰＬＬ回路
のブロツク図、第２図は第１図のグリツジ除去回
路の一実施例を示す回路図、第３図は第１図の位
相比較器の動作波形図、第４図、第５図は一般的
な従来のデイジタル位相比較器の回路図及び動作
波形図、第６図、第７図は一般的な従来のチヤー
ジポンプ回路の回路図及び動作波形図、第８図は
従来のＰＬＬ回路のブロツク図、第９図は第６図
の位相比較器の動作を示す波形図である。
図において、２０は位相比較器、２１はデイジ
タル位相比較器、２２はチヤージポンプ回路、３
０はローパスフイルタ、４０はＶＣＯ、５０はグ
リツジ除去回路を示す。なお、図中、同一符号は
同一、又は相当部分を示す。
Fig. 1 is a block diagram of a PLL circuit which is an embodiment of this invention, Fig. 2 is a circuit diagram showing an embodiment of the glitch removal circuit of Fig. 1, and Fig. 3 is a circuit diagram of the phase comparator of Fig. 1. Operating waveform diagrams; Figures 4 and 5 are circuit diagrams and operating waveforms of a general conventional digital phase comparator; Figures 6 and 7 are circuit diagrams and operating waveforms of a general conventional charge pump circuit. 8 is a block diagram of a conventional PLL circuit, and FIG. 9 is a waveform diagram showing the operation of the phase comparator shown in FIG. 6. In the figure, 20 is a phase comparator, 21 is a digital phase comparator, 22 is a charge pump circuit, and 3
0 is a low-pass filter, 40 is a VCO, and 50 is a glitch removal circuit. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
位相を比較し、その位相差を出力するデジタル位
相比較器２１と、この出力から細いパルス（グリ
ツジ）を除去するグリツジ除去回路５０と、その
出力を電流に変換するチヤージポンプ２２と、こ
の電流を積分し電圧変換するローパスフイルター
３０と、この電圧により位相を変化させる電圧制
御発振器４０で構成されるＰＬＬ回路において、
前記位相比較器にグリツジ除去回路を備えたこと
を特徴とするＰＬＬ回路。 A digital phase comparator 21 that compares the phases of the input signal A and the signal from the voltage controlled oscillator 40 and outputs the phase difference; a glitch removal circuit 50 that removes thin pulses (grids) from this output; In a PLL circuit composed of a charge pump 22 that converts the current into a current, a low-pass filter 30 that integrates this current and converts it into a voltage, and a voltage controlled oscillator 40 that changes the phase based on this voltage,
A PLL circuit characterized in that the phase comparator includes a glitch removal circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12344590U JPH0478827U (en) | 1990-11-20 | 1990-11-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12344590U JPH0478827U (en) | 1990-11-20 | 1990-11-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0478827U true JPH0478827U (en) | 1992-07-09 |
Family
ID=31871153
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12344590U Pending JPH0478827U (en) | 1990-11-20 | 1990-11-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0478827U (en) |
-
1990
- 1990-11-20 JP JP12344590U patent/JPH0478827U/ja active Pending
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