JPH048067A - Clock signal generating device - Google Patents

Abstract

PURPOSE:To avoid production of a defect in an interpolation signal of a horizontal scanning line due to jitter by adopting the constitution such that number of clock signals used for an access clock signal or the like of a video signal stored in a frame memory is limited to a prescribed number at all times for one horizontal period even when jitter takes place in the horizontal synchronizing signal. CONSTITUTION:An output signal of a processing section 60 and an output signal of a frame memory 10 are inputted to a liquid crystal display panel 30 via a switch section 20. A period when an output level of a counter 7 is at a high level is used for one horizontal period and a clock signal C is inputted to the frame memory 10 for the period. Thus, number of the clock signals C for one horizontal period is always limited to a prescribed number and even when jitter takes place in the horizontal synchronizing signal outputted from a synchronizing separator circuit 3, since number of the clock signals C for one horizontal period is always limited to a prescribed number in the frame memory 10, a defect of an interpolation signal due to jitter (such as loopback of one horizontal scanning line onto a next stage scanning line) is avoided.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a lock signal generating device suitable for installation in a liquid crystal display device in which frame display is performed on a liquid crystal display panel, for example.

[Summary of the Invention] The present invention relates to a lock signal generation device that is suitable for equipping, for example, a liquid crystal display device in which frame display is performed on a liquid crystal display panel. The number of clock signals used for the access clock signal etc. of the video signal is 1.
The configuration that always limits the number to a fixed number during the horizontal period avoids defects in the horizontal scanning line interpolation signal due to jitter, making it easy to perform appropriate interpolation and making the device more compact. , which allows for simplification.

[Conventional technology]

In a liquid crystal display device capable of frame display, interpolation of scanning lines is performed on the display panel, so when interpolating
The video signal for one frame is digitized and temporarily stored in a frame memory.

During interpolation, the video signal is read out from the frame memory and scanned, so the readout (access)
It is desirable that the number of clock signals serving as the timing is always constant within one horizontal period, and in this case, the clock signal can be obtained from an oscillator that is a constant multiple (for example, 4 fsc) of the horizontal synchronizing signal.

On the other hand, the horizontal synchronization signal, as understood from Fig. 2,
A standard signal has a fixed number of clock signals in one horizontal period (IH), but if jitter occurs due to uneven rotation of a VTR's rotating head, etc. (non-standard signal)
, the number of clock signals for IH increases.

As a result, defects due to jitter occur in the interpolated video signal, and proper interpolation is no longer performed.

Therefore, as understood from Fig. 3, the PLL circuit (10
When a horizontal synchronizing signal is input from the input terminal (200) of Input to the oscillator (V C0) (130), V C
The output of O(130) is output from the terminal (300) and is also outputted from P/n via the (1/n) frequency divider (I40).
C (110), which causes the output terminal (30
0), a horizontal synchronizing signal close to a standard signal is output.

[Problem to be solved by the invention]

However, when the PLL circuit (100) is used, it is difficult to adjust the VCO (130), etc., and the number of components increases, which hinders the miniaturization of the device and the number of elements. .

An object of the present invention is to provide a clock signal generation device that can easily perform proper scanning line interpolation by avoiding defects in interpolation signals due to jitter in horizontal synchronization signals, and can also be made smaller and simpler. Our goal is to provide the following.

[Means to solve the problem]

In order to achieve the above object, the clock signal generation device according to the present invention includes an oscillator ( 5), a counter (7) which counts the pulse signal (P) by a desired value and whose output level is set to high level in response to the counting; and the counter (7).
The condition is that the output level of is at a high level,
In response to the input of the pulse signal (P) of the oscillator (5), the gate circuit (9) outputs the input pulse signal (P) as a clock signal (C) for one horizontal period.
).

[Effect]

In the clock signal generation device according to the present invention, on the condition that the output level of the counter is set to high level, the number of pulse signals input to the gate circuit during that period is
This is the number of clock signals in one horizontal period.

〔Example〕

Hereinafter, preferred embodiments of the clock signal generation device according to the present invention will be described with reference to the drawings.

In FIG. 1, a clock signal generation device (1) includes a separation circuit (horizontal synchronization signal SE p ) that separates a horizontal synchronization signal from a composite video signal input from a terminal (50).
(3), an oscillator (5) and a counter (7) each receiving the output of the separation circuit (3).

The oscillator (5) is reset by the horizontal synchronizing signal input from the separation circuit (3), and generates and outputs a pulse signal (P) at a predetermined time interval (frequency is 4 fsc, for example), and outputs a pulse signal (P) to the counter (7). It is input to the negative input terminal (9a) of the AND gate circuit (9).

Then, the counter starts counting when the horizontal synchronizing signal is input from the separation circuit (3), counts the number of pulse signals (P) input from the oscillator (5), and calculates the count value. , for example, when the value reaches 480 (corresponding to the amount of processing in the next stage), counting is terminated.

Furthermore, when the counter (7) is counting, its output level is set to high level, and the AND gate circuit (
9) is input to the other terminal (9b).

Therefore, the output of the AND gate circuit (9) is the output of the counter (
7) Only during the period when the output level is high level,
The pulse signal is the same as the pulse signal (P), and this pulse signal is used as the access clock signal (C) of the frame memory (10), etc.

In this case, the composite video signal inputted from the terminal (50) is taken into the processing section (60), where the video signal is extracted, digitized, etc., and taken into the frame memory (10).

The output signal of the processing section (60) and the output signal of the frame memory (step 0) are input to the liquid crystal display panel (30) via the switch section (20).

Note that the switch section (20) switches between parallel connection and cross connection for each field in accordance with the input signal (vertical synchronization signal, etc.) from the processing section (60), and outputs the video signal (
(odd) and the interpolation signal (output signal of the frame memory (10); even).

As described above, in this embodiment, one horizontal period is defined as the output level of the counter (7) being at a high level, and the clock signal (C) is input to the frame memory (10) during this period.

Therefore, the number of clock signals (C) in one horizontal period is always limited to a fixed number (that is, has an upper limit), and even if jitter occurs in the horizontal same signal output from the separation circuit (3). Also, since the number of access clock signals (C) of the frame memory (10) is limited to a certain number, defects in the interpolation signal due to jitter (for example, one horizontal scanning line is folded back onto the next scanning line). is avoided.

As a result, appropriate interpolation can be easily performed.

In addition, the configuration is simpler than one that uses a PLL circuit (100), and the device (1) can be configured with only a digital IC, so the number of parts in the device (1) can be reduced and the device can be made smaller. , simplification is possible.

Note that the clock signal (C) can be used as various clock signals for a liquid crystal display device equipped with the device (1).

〔Effect of the invention〕

As can be understood from the above explanation, in the clock signal generation device according to the present invention, provided that the output level of the counter is high level, the number of pulse signals input to the gate circuit during that period is , ■ The number of clock signals in the horizontal period.

Therefore, even if jitter occurs in the horizontal synchronizing signal separated from the composite video signal, the number of clock signals within the horizontal period is limited to a fixed number.

As a result, the number of clock signals when accessing the video signal for one frame stored in the frame memory is limited to a certain number, so that defects due to jitter do not occur in the interpolated signal of the scanning line. Appropriate interpolation can be easily performed.

Also, compared to conventional PLL circuits,
Since adjustment is easy, good interpolation processing can be maintained, and the number of parts can be reduced, for example, by using only a digital IC, so that the device can be made smaller and simpler.

[Brief explanation of drawings]

FIG. 1 is an overall schematic configuration diagram of a preferred embodiment of a clock signal generation device according to the present invention, FIG. 2 is a timing chart showing the relationship between a horizontal synchronization signal and a clock signal, and FIG. 3 is a diagram of a conventional clock signal generation device. It is a block diagram of an example. (1) is a clock signal generation device, (3) is a separation circuit, (
5) is an oscillator, (7) is a counter, (9) is an AND gate circuit, (10) is a frame memory, and (30) is a liquid crystal display panel.

Claims (1)

[Claims] An oscillator that can be reset by a horizontal synchronizing signal separated from a composite video signal and outputs pulse signals at predetermined time intervals; A counter whose output level is high in response to counting, and a counter whose output level is high in response to the input of the pulse signal of the oscillator, provided that the output level of the counter is high. A clock signal generation device comprising: a gate circuit for outputting the input pulse signal as a clock signal for one horizontal period.