JPH048159U - - Google Patents
Info
- Publication number
- JPH048159U JPH048159U JP5001590U JP5001590U JPH048159U JP H048159 U JPH048159 U JP H048159U JP 5001590 U JP5001590 U JP 5001590U JP 5001590 U JP5001590 U JP 5001590U JP H048159 U JPH048159 U JP H048159U
- Authority
- JP
- Japan
- Prior art keywords
- port
- microprocessor
- signal
- ram
- sam
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Multi Processors (AREA)
Description
第１図は本考案の一実施例の構成ブロツク図、
第２図及び第３図は動作の一例を示すタイムチヤ
ートである。
１……ビデオＲＡＭ、ＤＢ……データバス、２
……第１のマイクロプロセツサ（または通信コン
トローラ）、３……第２のマイクロプロセツサ、
４……ＳＡＭポート方向保持手段、５……アクセ
ス信号発生手段。
FIG. 1 is a block diagram of an embodiment of the present invention.
FIGS. 2 and 3 are time charts showing an example of the operation. 1...Video RAM, DB...Data bus, 2
...first microprocessor (or communication controller), 3...second microprocessor,
4... SAM port direction holding means, 5... Access signal generation means.
Claims (1)
ランダムアクセスポート（ＲＡＭポート）とを有
するビデオＲＡＭのメモリ制御回路であつて、 第１のデータバスを介して前記ビデオＲＡＭに
アクセスする第１のマイクロプロセツサと、 第２のデータバスを介して前記ビデオＲＡＭに
アクセスする第２のマイクロプロセツサと、 前記第２のマイクロプロセツサからのリード／
ライト信号と、前記ＳＡＭポート／ＲＡＭポート
間のデータ転送のためのセレクト信号を入力し、
これらの信号から第２のマイクロプロセツサがＳ
ＡＭ／ＲＡＭ間のデータ転送を行つていることを
検出すると共に、この時のリード／ライト信号に
よりＳＡＭポート方向を保持するＳＡＭポート方
向保持手段と、 このＳＡＭポート方向保持手段からの信号と、
第１のマイクロプロセツサ２からのリード／ライ
ト信号と、アクセス要求（セレクト信号）とを入
力し、これらの信号からデータバス上での衝突が
ないか判定し、正常のときにのみ前記ＳＡＭポー
トにアクセス信号を出力するアクセス信号発生手
段と を備えたことを特徴とするメモリ制御回路。[Scope of utility model registration claim] Serial access port (SAM port),
a memory control circuit for a video RAM having a random access port (RAM port); a first microprocessor accessing the video RAM via a first data bus; a second microprocessor that accesses the video RAM; and a read/write from the second microprocessor.
inputting a write signal and a select signal for data transfer between the SAM port/RAM port;
From these signals, a second microprocessor
A SAM port direction holding means that detects that data is being transferred between AM/RAM and holds the SAM port direction based on a read/write signal at this time; a signal from the SAM port direction holding means;
A read/write signal and an access request (select signal) from the first microprocessor 2 are input, and based on these signals, it is determined whether there is a collision on the data bus, and only when the data bus is normal, the SAM port is and access signal generation means for outputting an access signal to the memory control circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5001590U JPH0751633Y2 (en) | 1990-05-14 | 1990-05-14 | Memory control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5001590U JPH0751633Y2 (en) | 1990-05-14 | 1990-05-14 | Memory control circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH048159U true JPH048159U (en) | 1992-01-24 |
| JPH0751633Y2 JPH0751633Y2 (en) | 1995-11-22 |
Family
ID=31568201
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5001590U Expired - Lifetime JPH0751633Y2 (en) | 1990-05-14 | 1990-05-14 | Memory control circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0751633Y2 (en) |
-
1990
- 1990-05-14 JP JP5001590U patent/JPH0751633Y2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0751633Y2 (en) | 1995-11-22 |
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