JPH0481876B2 - - Google Patents
Info
- Publication number
- JPH0481876B2 JPH0481876B2 JP59265456A JP26545684A JPH0481876B2 JP H0481876 B2 JPH0481876 B2 JP H0481876B2 JP 59265456 A JP59265456 A JP 59265456A JP 26545684 A JP26545684 A JP 26545684A JP H0481876 B2 JPH0481876 B2 JP H0481876B2
- Authority
- JP
- Japan
- Prior art keywords
- tunnel barrier
- superconductor electrode
- superconductor
- forming
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000002887 superconductor Substances 0.000 claims description 34
- 238000000034 method Methods 0.000 claims description 32
- 230000004888 barrier function Effects 0.000 claims description 30
- 238000005530 etching Methods 0.000 claims description 20
- 239000010955 niobium Substances 0.000 description 15
- 239000000758 substrate Substances 0.000 description 8
- 238000000992 sputter etching Methods 0.000 description 5
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 239000000470 constituent Substances 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- GQPLMRYTRLFLPF-UHFFFAOYSA-N Nitrous Oxide Chemical compound [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- MVPPADPHJFYWMZ-UHFFFAOYSA-N chlorobenzene Chemical compound ClC1=CC=CC=C1 MVPPADPHJFYWMZ-UHFFFAOYSA-N 0.000 description 2
- 239000005416 organic matter Substances 0.000 description 2
- 239000003960 organic solvent Substances 0.000 description 2
- 101100269850 Caenorhabditis elegans mask-1 gene Proteins 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 229910052758 niobium Inorganic materials 0.000 description 1
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 239000001272 nitrous oxide Substances 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N60/00—Superconducting devices
- H10N60/01—Manufacture or treatment
- H10N60/0912—Manufacture or treatment of Josephson-effect devices
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Superconductor Devices And Manufacturing Methods Thereof (AREA)
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明はジヨセフソン接合素子の形成方法に関
し、さらに詳しくは微細な接合の作製に適したジ
ヨセフソン接合素子の形成方法に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a method for forming a Josephson junction element, and more particularly to a method for forming a Josephson junction element suitable for producing fine junctions.
（従来技術の問題点）
従来、ジヨセフソン接合素子で構成される集積
回路の製造では、接合特性の制御に最も重要なト
ンネル障壁部を規定する主な技術はリフトオフ法
であつた。この一例として、アール・エフ・ブル
ーム（R.F.Broom）らによつて1980年10月に発
表されたアイ・イー・イー・イー・トランズアク
シヨンズ・オン・エレクトロン・デバイシーズ
（IEEE Transaction on Electron Devices）の
第ED−27巻第10号1998〜2008頁の論文がある。
この方法を第２図ａ〜ｃを用いて工程順に説明す
る。第２図ａに示すように、絶縁体基板２１上に
形成された第１の超伝導体電極２２上のトンネル
障壁部となる部分にアンダーカツト形状のレジス
トマスク２３を形成し、第２図ｂに示すように基
板表面に絶縁体層２４を蒸着し、引き続きリフト
オフすると第２図ｃに示すような開口部をもつト
ンネル障壁部が形成される。この方法は、アンダ
ーカツト形状のレジストマスク２３は通常のホト
レジスト工程に加え、露光前にクロロベンゼンな
どの有機溶剤に浸すことによつて得られるが、マ
スク寸法やマスク形状はレジストのブリベーク条
件や有機溶剤の液温、デイツブ時間などの影響を
受けやすい。特に、トンネル障壁部の有効面積を
規定するレジストマスク２３下部の寸法を精度よ
く得ることは非常に難しい。また、トンネル障壁
部がこの形成過程で直接大気にさらされたり、レ
ジスト処理を受けることにより汚染されるという
問題もある。(Problems with the Prior Art) Conventionally, in the manufacture of integrated circuits composed of Josephson junction elements, the lift-off method has been the main technique for defining the tunnel barrier section, which is most important for controlling junction characteristics. An example of this is the IEEE Transaction on Electron Devices, published in October 1980 by RFBroom et al. There are papers in ED-27, No. 10, pages 1998-2008.
This method will be explained step by step using FIGS. 2a to 2c. As shown in FIG. 2a, an undercut-shaped resist mask 23 is formed on the first superconductor electrode 22 formed on the insulating substrate 21 at a portion that will become the tunnel barrier portion, and as shown in FIG. As shown in FIG. 2C, an insulating layer 24 is deposited on the surface of the substrate and then lifted off to form a tunnel barrier section having an opening as shown in FIG. 2C. In this method, the undercut-shaped resist mask 23 is obtained by immersing it in an organic solvent such as chlorobenzene before exposure in addition to the normal photoresist process, but the mask dimensions and mask shape are determined by the resist pre-bake conditions and the organic solvent. It is easily affected by liquid temperature, date time, etc. In particular, it is very difficult to accurately obtain the dimensions of the lower part of the resist mask 23 that defines the effective area of the tunnel barrier section. There is also the problem that the tunnel barrier section is directly exposed to the atmosphere during this formation process or becomes contaminated when subjected to resist treatment.
一方、上記問題点を解決する方法として、エツ
チング法でトンネル障壁部を規定する方法があ
る。たとえば、東海林彰らによつて発表されたア
プライド・フイジクス・レターズ（Appl.Phys.
Lett.）第41巻、1982年、1097〜1099頁の論文が
ある。この方法の工程を第３図ａ〜ｃに示す。第
３図ａのように、絶縁体基板３１上に第１の超伝
導体電極３２、トンネル障壁層３３、第２の超伝
導体電極３４の３層膜から成る接合構成層を形成
する。次に、第３図ｂに示すように、第２の超伝
導体電極３４上のトンネル障壁部となる場所に通
常のホトレジスト工程でレジストマスク３５を形
成した後、第３図ｃのように反応性スパツタエツ
チング法により第２の超伝導体電極３４のレジス
トマスク以外の箇所を選択的にエツチング除去し
てトンネル障壁部を形成する。この方法では、リ
フトオフ法のようにレジストマスクをアンダーカ
ツト形状にする必要がないため、比較的精度の良
いレジストマスクを用いることができ、トンネル
障壁部の寸法精度も向上する。しかしながら、上
記レジストマスクでもパターン寸法が１〜2μｍ
程度まで微細化されると、レジストマスクコーナ
ー部の解像性の、再現性の問題がクローズアツプ
される。特に、ジヨセフソン接合素子では、トン
ネル障壁部の面積が接合特性に大きく影響するた
め、これは重要な問題となる。 On the other hand, as a method for solving the above-mentioned problems, there is a method of defining the tunnel barrier portion by an etching method. For example, Applied Physics Letters (Appl.Phys.
Lett.) Volume 41, 1982, pages 1097-1099. The steps of this method are shown in Figures 3a-c. As shown in FIG. 3a, a junction constituent layer consisting of a three-layer film of a first superconductor electrode 32, a tunnel barrier layer 33, and a second superconductor electrode 34 is formed on an insulator substrate 31. Next, as shown in FIG. 3b, a resist mask 35 is formed on the second superconductor electrode 34 at a location that will become the tunnel barrier portion by a normal photoresist process, and then a reaction process is performed as shown in FIG. 3c. A tunnel barrier portion is formed by selectively etching away portions of the second superconductor electrode 34 other than the resist mask using a natural sputter etching method. In this method, unlike the lift-off method, there is no need to make the resist mask into an undercut shape, so a resist mask with relatively high precision can be used, and the dimensional precision of the tunnel barrier portion can also be improved. However, even with the above resist mask, the pattern size is 1 to 2 μm.
When the resist mask is miniaturized to a certain extent, the problem of resolution and reproducibility of the corner portion of the resist mask becomes more prominent. In particular, in Josephson junction devices, the area of the tunnel barrier greatly affects the junction characteristics, so this is an important issue.
（発明の目的）
本発明は、このような従来の欠点を取り除いた
ジヨセフソン接合素子の形成方法を提供すること
にある。(Object of the Invention) An object of the present invention is to provide a method for forming a Josephson junction element that eliminates such conventional drawbacks.
（発明の構成）
本発明によれば、基板上の第１の超伝導体電極
Nbの一表面上のトンネル障壁層AlOx、およびこ
のトンネル障壁層を介して前記第１の超伝導体電
極と対向する第２の超伝導体電極Nbを有するジ
ヨセフソン接合素子の形成方法において、基板上
に第１の超伝導体電極、この第１の超伝導体電極
上にトンネル障壁層、このトンネル障壁層上に第
２の超伝導体電極を連続形成する工程、前記第２
の超伝導体電極上にストライプ状のエツチングマ
スクを形成し、前記第２の超伝導体電極の前記エ
ツチングマスク以外の箇所を選択的にエツチング
し、前記エツチングマスクを剥離した後、前記第
２の超伝導体電極と交差するストライプ状のエツ
チングマスクを形成し、前記第２の超伝導体電極
の露出箇所を完全にエツチングしてトンネル障壁
部を規定する工程を含むことを特徴とするジヨセ
フソン接合素子の形成方法が得られる。(Structure of the Invention) According to the present invention, the first superconductor electrode on the substrate
In a method for forming a Josephson junction element having a tunnel barrier layer AlO x on one surface of Nb, and a second superconductor electrode Nb facing the first superconductor electrode via the tunnel barrier layer, the substrate a step of successively forming a first superconductor electrode on top, a tunnel barrier layer on the first superconductor electrode, and a second superconductor electrode on the tunnel barrier layer;
forming a striped etching mask on the superconductor electrode, selectively etching portions of the second superconductor electrode other than the etching mask, and peeling off the etching mask; A Josephson junction device comprising the step of forming a striped etching mask that intersects with the superconductor electrode and completely etching the exposed portion of the second superconductor electrode to define a tunnel barrier section. A method of forming is obtained.
（構成の詳細な説明）
本発明では、互いに交差する複数のストライプ
状のエツチングマスクによりトンネル障壁部を規
定するため、シヤープなコーナー部をもつ高精度
のトンネル障壁部パターンの形成が可能となる。(Detailed Description of Structure) In the present invention, since the tunnel barrier section is defined by a plurality of mutually intersecting striped etching masks, it is possible to form a highly accurate tunnel barrier section pattern with sharp corner sections.
（実施例）
次に本発明を実施例を参照して詳細に説明す
る。(Examples) Next, the present invention will be described in detail with reference to Examples.
第１図ａに示すように、絶縁体基板１１上に第
１の超伝導体電極１２、トンネル障壁層１３、第
２の超伝導体電極１４からなる接合構成層を形成
する。たとえば、表面を熱酸化二酸化ケイ素
（SiO2）が被覆したシリコン（Si）基板上に、ス
パツタ法によりニオブ（Nb）膜2000Å、アルミ
ニウム（Al）膜約20Åを連続被着した後、Al膜
を熱酸化して酸化膜を形成し、引き続きNb膜
2000Åをスパツタ蒸着する。この膜上に、通常の
ホトレジスト工程でレジストマスクを形成し、フ
ロン１３（CF4）をエツチングガスとして用いた
反応性スパツタエツチング法でNb／Al酸化物／
Nbを完全にエツチングし、３層膜からなる接合
構成層を形成する。次に、第１図ｂに示すよう
に、３層膜上に形成したストライプ状のレジスト
マスク１５を通して、たとえばCF4を用いた反応
性スパツタエツチング法で第２の超伝導体電極１
４を選択的にエツチングする。レジストマスク１
５を剥離した後、第１図ｃに示すように、第２の
超伝導体電極１４パターンと交差するようにスト
ライプ状のレジストマスク１５′を形成し、第１
図ｂと同様な方法で第２の超伝導体電極１４の露
出部分を選択エツチングし、第１図ｄに示すよう
なトンネル障壁部を形成する。AlやAl酸化物に
対するNbのエツチング速度比として100程度が得
られるためめ、Al／Al酸化物上のNbの選択エツ
チングが可能である。本プロセスで形成したトン
ネル障壁部の寸法精度は単一のレジストマスクを
用いた場合に比べ大幅に改善された。これは、主
として第２の超伝導体電極１４パターンのコーナ
ー部の解像性が向上したことによる。また、スト
ライプ状のレジストマスクを用いることにより、
現象時にレジストマスクがより安定に保持され
た。 As shown in FIG. 1a, a junction constituent layer consisting of a first superconductor electrode 12, a tunnel barrier layer 13, and a second superconductor electrode 14 is formed on an insulator substrate 11. As shown in FIG. For example, on a silicon (Si) substrate whose surface is coated with thermally oxidized silicon dioxide (SiO 2 ), a niobium (Nb) film of 2000 Å and an aluminum (Al) film of approximately 20 Å are successively deposited by sputtering, and then an Al film is applied. Thermal oxidation forms an oxide film, followed by a Nb film.
Sputter deposit 2000Å. A resist mask is formed on this film using a normal photoresist process, and Nb/Al oxide/Nb/Al oxide/
The Nb is completely etched to form a bonding layer consisting of three layers. Next, as shown in FIG. 1b, the second superconductor electrode 1 is etched by reactive sputter etching using, for example, CF 4 through a striped resist mask 15 formed on the three-layer film.
4 is selectively etched. resist mask 1
5, a striped resist mask 15' is formed so as to intersect the pattern of the second superconductor electrode 14, as shown in FIG.
The exposed portion of the second superconductor electrode 14 is selectively etched using a method similar to that shown in FIG. 1B to form a tunnel barrier portion as shown in FIG. 1D. Since the etching rate ratio of Nb to Al or Al oxide is about 100, selective etching of Nb on Al/Al oxide is possible. The dimensional accuracy of the tunnel barrier formed by this process was significantly improved compared to when a single resist mask was used. This is mainly due to the improved resolution of the corner portions of the second superconductor electrode 14 pattern. In addition, by using a striped resist mask,
The resist mask was held more stably during the phenomenon.
上記工程はトンネル障壁部を規定する工程であ
るが、ジヨセフソン接合素子を作製するために
は、さらに一例として次に示すような上部電極配
線を形成する工程が必要である。レジストマスク
を剥離した後、シラン（SiH4）と亜酸化窒素
（N2O）の混合ガスを用いたプラズマCVD法で
SiO2膜3000Åを被着する。引き続き有機物
（AZ1350J）8000Åをスピン塗布し、窒素雰囲気
中200℃でベーク処理する。次に、上記SiO2と有
機物のエツチング速度が等しくなるようにビーム
入射角を設定したイオンミリング法により、上層
Nb表面まで有機物、SiO2をエツチングする。露
出したNb表面をArでスパツタクリーニングした
後、Nb膜3000Åをスパツタ蒸着し、下部電極配
線の形成と同様な方法で上部電極配線を形成す
る。 The above process is a process for defining a tunnel barrier portion, but in order to fabricate a Josephson junction element, a further process for forming an upper electrode wiring as shown below is required as an example. After removing the resist mask, it is processed using a plasma CVD method using a mixed gas of silane (SiH 4 ) and nitrous oxide (N 2 O).
Deposit a SiO 2 film of 3000 Å. Subsequently, an organic material (AZ1350J) of 8000 Å is applied by spin coating and baked at 200°C in a nitrogen atmosphere. Next, the upper layer was etched using an ion milling method in which the beam incidence angle was set so that the etching rate of the SiO 2 and the organic matter were equal.
Etch organic matter and SiO 2 to the Nb surface. After sputter cleaning the exposed Nb surface with Ar, a 3000 Å Nb film is sputter-deposited, and the upper electrode wiring is formed in the same manner as the lower electrode wiring.
本実施例では、接合構成層としてNb／Al酸化
物／Nbを用いた場合について説明したが、第２
の超伝導体電極が第１の超伝導体電極あるいはト
ンネル障壁層に対して選択的にエツチングされる
ならば、任意の接合構成層の組合せが適用でき
る。超伝導体電極の加工法としては、反応性スパ
ツタエツチング法以外にも、接合構成層の組合せ
に応じてイオンミリング法などの他の方法も使用
できる。また、エツチングマスクには、有機レジ
スト、無機レジスト、さらにはこれらのレジスト
の転写により形成した、よりエツチング耐性のあ
る金属マスクなども用いることができる。 In this example, the case where Nb/Al oxide/Nb was used as the bonding layer was explained.
Any combination of junction constituent layers is applicable, provided that the superconductor electrodes are selectively etched with respect to the first superconductor electrode or the tunnel barrier layer. In addition to reactive sputter etching, other methods such as ion milling may be used to process the superconductor electrode depending on the combination of bonding layers. Further, as the etching mask, an organic resist, an inorganic resist, or a metal mask formed by transferring these resists and having higher etching resistance can be used.
（発明の効果）
以上説明したように本発明のよれば、解像性や
再現性の良いパターン形成が可能なため、微細で
寸法精度の優れたトンネル障壁部をもつジヨセフ
ソン接合素子を形成することができる。(Effects of the Invention) As explained above, according to the present invention, it is possible to form a pattern with good resolution and reproducibility, so it is possible to form a Josephson junction element having a fine tunnel barrier portion with excellent dimensional accuracy. I can do it.
第１図ａ〜ｄは本発明のジヨセフソン接合素子
の形成方法を説明するための主要工程における素
子の斜視図、第２図ａ〜ｃ、第３図ａ〜ｃは従来
のジヨセフソン接合素子の形成方法を工程順に説
明するための断面図である。
図において、１１，２１，３１を基板、１２，
２２，３２は第１の超伝導体電極、１３，３３は
トンネル障壁層、１４，３４は第２の超伝導体電
極、１５，１５′，２３，３５はレジストマスク、
２４は絶縁体層である。
Figures 1 a to d are perspective views of the device in main steps for explaining the method for forming a Josephson junction element of the present invention, and Figures 2 a to c and 3 a to c are conventional formation of a Josephson junction element. FIG. 3 is a cross-sectional view for explaining the method step by step. In the figure, 11, 21, 31 are substrates, 12,
22, 32 are first superconductor electrodes, 13, 33 are tunnel barrier layers, 14, 34 are second superconductor electrodes, 15, 15', 23, 35 are resist masks,
24 is an insulator layer.
Claims (1)
の超伝導体電極の一表面上のトンネル障壁層
AlOx、およびこのトンネル障壁層を介して前記
第１の超伝導体電極に対向する第２の超伝導体電
極Nbを有するジヨセフソン接合素子の形成方法
において、基板上に第１の超伝導体電極、この第
１の超伝導体電極上にトンネル障壁層、このトン
ネル障壁層上に第２の超伝導体電極を連続形成す
る工程、前記第２の超伝導体電極上にストライプ
状のエツチングマスクを形成し、前記第２の超伝
導体電極の前記エツチングマスク以外の箇所を選
択的にエツチングし、前記エツチングマスクを剥
離した後、前記第２の超伝導体電極と交差するス
トライプ状のエツチングマスクを形成し、前記第
２の超伝導体電極の露出箇所を完全にエツチング
して、トンネル障壁部を規定する工程を含むこと
を特徴とするジヨセフソン接合素子の形成方法。1 The first superconductor electrode Nb and this first
tunnel barrier layer on one surface of the superconductor electrode of
In the method for forming a Josephson junction element having AlO , a step of successively forming a tunnel barrier layer on the first superconductor electrode and a second superconductor electrode on the tunnel barrier layer, and forming a striped etching mask on the second superconductor electrode. After selectively etching the second superconductor electrode other than the etching mask and peeling off the etching mask, a stripe-shaped etching mask intersecting with the second superconductor electrode is formed. A method of forming a Josephson junction device comprising the steps of forming a tunnel barrier and completely etching exposed portions of the second superconductor electrode to define a tunnel barrier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59265456A JPS61144084A (en) | 1984-12-18 | 1984-12-18 | Forming method of josephson junction element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59265456A JPS61144084A (en) | 1984-12-18 | 1984-12-18 | Forming method of josephson junction element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61144084A JPS61144084A (en) | 1986-07-01 |
| JPH0481876B2 true JPH0481876B2 (en) | 1992-12-25 |
Family
ID=17417416
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59265456A Granted JPS61144084A (en) | 1984-12-18 | 1984-12-18 | Forming method of josephson junction element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61144084A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6394692A (en) * | 1986-10-09 | 1988-04-25 | Agency Of Ind Science & Technol | Manufacture of josephson junction device |
| JP6254032B2 (en) * | 2014-03-28 | 2017-12-27 | 住友重機械工業株式会社 | SNS type Josephson junction element manufacturing method and SNS type Josephson junction element manufacturing apparatus |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58175830A (en) * | 1982-04-08 | 1983-10-15 | Matsushita Electric Ind Co Ltd | Forming method for pattern |
| US4432134A (en) * | 1982-05-10 | 1984-02-21 | Rockwell International Corporation | Process for in-situ formation of niobium-insulator-niobium Josephson tunnel junction devices |
-
1984
- 1984-12-18 JP JP59265456A patent/JPS61144084A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61144084A (en) | 1986-07-01 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |