JPH0482082A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To enable the compression/extension processing of temporarily stored data at a high speed by providing an input/output circuit part including a compression circuit and an extension circuit for data to be connected to at least one port in a random access memory part with a multiport and a control means controlling these. CONSTITUTION:The semiconductor memory device is constructed by including a random access memory part 1 with the multiport, an input/output circuit part 4 including a compression circuit 2 and an extension circuit 3 for the data to be connected to at least one port in this, and a control part 5 deciding the operation mode of the input/output circuit part 4 by an external control signal in one semiconductor substrate. Therefore, the compression/extension processing can be performed only by the internal data transmission control between the random access memory part 1 and the built-in control means 5 by the random access memory part 1 and the compression/extension circuits 2, 3 corporated in the common semiconductor substrate. Thus, the compression/ extension processing is speeded up while equipping continuity with the temporary storage of the data and the compression/extension processing of the data.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multi-port semiconductor memory device and additional functions thereof, and relates to a technique that is effective when applied to, for example, a buffer memory for communication data.

[Conventional technology]

The amount of information per pixel, such as image information, is extremely large compared to code information, so in facsimile systems, for example, the amount of information to be transmitted is compressed to shorten the data transmission time. . As this data compression method, there is a one-dimensional encoding method. This method is a method in which each pixel block specified by binary information is encoded.

By the way, when compressing data after temporarily storing information before encoding in a data buffer, at least access the data buffer, read the necessary data, and compress the read data. The encoding process for this must be performed via software or the like. The same holds true when compressed data is expanded and restored. That is, conventional data buffers are not equipped with data compression/expansion functions.

Examples of documents describing one-dimensional encoding methods include "Microcomputer Handbook" published by Ohmsha on December 25, 1985, pages 1019 and 102.
There are 0 pages.

In addition, as an invention having a means for compressing data on the same chip as a memory, the patent application publication number 1983-
183699 and patent application publication number Sho 63-204594
There is.

[Problem to be solved by the invention]

If the data buffer memory is not equipped with a data compression/decompression function as in the past, the temporary storage of data and the compression/decompression processing for that data are separated, so the data buffer memory and compression/decompression are External data transfer must be performed to and from the circuit that performs compression/
When the decompression process is performed via software, the load on the processor increases, and as a result, it takes time to compress/decompress the temporally stored data, reducing the operating efficiency of the system.

An object of the present invention is to provide a semiconductor memory device that can temporarily store data and perform data compression/expansion processing.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a random access memory section having a multi-port, an input/output circuit section including a data compression circuit and an expansion circuit connected to at least one port of the random access memory section,
a control means for determining the operation mode of the random access memory section and the input/output circuit section according to an external control signal;
A semiconductor memory device is constructed by including the semiconductor memory device in one semiconductor substrate.

When using the random access memory section as an area to temporarily store data before being compressed, in order to enable at least one port to exchange compressed data with the outside, the random access memory section must be There are two operating modes: one in which the data read from the memory is compressed and serially output to the outside, and the other in which the data supplied from the outside is decompressed and written to the random access memory section.
It should be included in the operation mode determined by the control means.
.

In addition, when using the random access memory section as an area for temporarily storing compressed data, in order to enable at least one port to exchange uncompressed normal data with the outside, random An operation mode in which data read from the memory section is expanded and output to the outside, and an operation mode in which data supplied from the outside is compressed and written to the random access memory section.
It may be included in the operation mode determined by the control means.

Furthermore, when a one-dimensional encoding method is adopted for data compression/decompression processing, it is desirable to connect the compression circuit and decompression circuit to the serial access port of the random access memory section. When operational flexibility is considered, the other ports in the random access memory section may be made into parallel access ports connectable to the data bus.

Furthermore, in order to increase the uses of the semiconductor memory device of the present invention, it is preferable that the operation modes determined by the control means further include an operation mode in which data read from the serial access port of the random access memory section is serially output as is. .

[For production]

According to the above means, the compression circuit/expansion circuit built into a common semiconductor substrate together with the random access memory section can perform compression/expansion processing only by internal data transfer control between the built-in control means and the random access memory section. This enables continuity in temporary data storage and data compression/decompression processing.
Achieve faster compression/decompression processing.

〔Example〕

FIG. 1 shows an embodiment of a semiconductor memory device according to the present invention. The semiconductor memory device 52 of this embodiment is formed on a single semiconductor substrate such as silicon by a known semiconductor integrated circuit manufacturing technique, and has a ground voltage GND and a ground voltage for operating each circuit in the device. Voltage V higher than voltage
It has two power supply voltage terminals to which CC is supplied and includes a random access memory section 1 having a multi-port, a compression circuit 2 and an expansion circuit 3, and an input circuit that is serially interfaced between the random access memory section 1 and the outside. Output circuit section 4
and a controller 5 that performs internal timing control and mode setting control.

The random access memory section 1 has a structure similar to a frame buffer memory or video RAM for image data with dual ports, although it is not particularly limited, and has a plurality of dynamic memory blocks each consisting of an MO5FET for address selection and a capacitor for information storage. The memory cell array 10 includes memory cells MC arranged in a matrix. 1
1 is a row address decoder, and a memory cell array 10
A selection terminal of a memory cell MC included in the word line selects one of a plurality of word lines WL, .about.WL connected row by row. A plurality of bit lines DLl to DLa, to which data input/output terminals of memory cells MC are coupled column by column, are coupled to a sense amplifier SA and a precharge circuit PC on one side, and are connected in parallel with a column selection switch circuit 12 on the other side. Parallel data external terminal DP via input/output circuit 13
Connected to 0~Dpy. The column selection switch circuit 12
is switch-controlled by the output signal of the column address decoder 14. Here, the parallel input/output circuit 13 is an example of a parallel access port for inputting and outputting parallel data, and is used for random access.

In FIG. 1, reference numeral 16 denotes an address buffer and an address multiplexer to which external address signals AR and AC each consisting of a plurality of bits are supplied, and supplies an internal row address signal ar to the row address decoder 11 according to a predetermined timing. , internal column address signal aQ to the column address decoder 14 according to a predetermined timing.
supply.

The random access memory section 1 has a data register and selector 17 connected to bit lines DL-DL as an example of a serial access port, and a parallel data transfer gate 18 is interposed at the front stage thereof. The parallel data transfer gate 18 causes the data register and selector 17 to latch one row of data read from the memory cell array 10 in an internal data transfer cycle that is alternatively selected between the random access cycle and the internal data transfer cycle. The data register and selector 17 sequentially outputs the latched data serially from a predetermined bit position for the bit array. Further, the data register and selector 17 latches the serial data supplied from the input/output circuit section 4, and applies the latched data to the bit line via the parallel data transfer gate 18. In other words, the data register and selector 17 are the memory cell array 1
Parallel/serial conversion of data is performed between the input/output circuit section 4 and the input/output circuit section 4.

Such serial data input/output control is performed based on the operations of the serial address counter 20 and the serial decoder 19 that decodes its output. That is, the serial address counter 2o receives the internal column address signal ac in an internal data transfer cycle (data transfer cycle between the random access memory section 1 and the input/output circuit section 4).
is taken in as preset data, serial addresses are generated in order from the position of the column address corresponding to this preset data, and the serial decoder 19 decodes this to input and output serial data in order.

The serial address counter 20 also receives a reset signal φ10. which will be described later. When supplied, a serial address for designating a certain fixed column address position is generated, and the column address is incremented in synchronization with the supplied serial clock φ4IC, which will be described later.

The input/output circuit section 4 is a first circuit that exchanges uncompressed data (hereinafter simply referred to as normal data) with the outside.
It has a serial input/output circuit 21 and a second serial input/output circuit 22 for exchanging compressed data with the outside, and a selection circuit 23 selects connection to the data register and selector 17. And the compression circuit 2
compresses the data provided from the first serial input/output circuit 21 and supplies it to the second serial data external terminal I)ax via the second serial input/output circuit 22. Further, the expansion circuit 3 expands the data provided from the second serial input/output circuit 22 and supplies the expanded data to the first serial data external terminal I)it via the first serial input/output circuit 21. Here, the first and second serial input/output circuits 21 and 22 include a storage means for storing data in a serial in/serial out format, and a gate for selecting the input/output direction and the input/output edge of the data. The simplest configuration can be configured by serial-in/serial-out type registers and selectors, or it can be configured by serial access memory.

The data compression/expansion method performed by the compression circuit 2 and the expansion circuit 3 can be, for example, a -dimensional encoding/encoding method.

The controller 5 receives external control signals such as a row address strobe signal RAS, a column address strobe signal W, a write enable signal W, a data transfer signal D, and a data receive signal D.
R, mode signal M0DEL, MODE2. A serial clock φ3° and a serial clock φ43G obtained by dividing the frequency of the serial clock φ3c by four are respectively supplied to predetermined control signal terminals. The controller 5 identifies the operation mode based on the various control signals supplied above, and forms various timing signals corresponding to the operation mode.

Row address strobe signal RAS- is regarded as a chip selection signal, and internal circuits are activated in response to its low level. Also, this row address strobe signal πAS
is the column address strobe signal and is used together with λ100 to control address multiplexing of the row address signal and column address signal. The write enable signal WE is a control signal for instructing whether random access via the parallel input/output circuit 13 is a read operation or a write operation.

The random access cycle is enabled on the condition that both the data transfer signal 100 and the data receive signal 100 are negated to a high level. The data transfer signal is regarded as an instruction signal for data output operation between the input/output circuit section 4 and the outside.

The data receive signal ■π is regarded as an instruction signal for data input operation between the input/output circuit section 4 and the outside. The mode signals MODEL and MODE2 are mode setting signals for determining the compression/expansion operation and the operation of the serial input/output circuits 21 and 22 when the data transfer signal DT or the data receive signal 10 is asserted. . When the data transfer signal Hyakucho and the data receive signal Hyakucho are both set to low level, the controller 5 outputs the reset signal φ16. Form and compress times $
2. The data is supplied to the decompression circuit 3 and the serial address counter 20.

FIG. 2 shows a block diagram of an example of a compression circuit 2 for realizing a one-dimensional encoding method.

The compression circuit 2 will be explained below.

The compression circuit 2 receives a reset signal φ10. ．． Serial clock φIcy Serial clock φ4. which is the frequency of serial clock φ1c divided by 4. c and normal data are supplied.

The D-type latch circuit 25 latches normal data sequentially supplied in synchronization with the serial clock φ45C. High level reset signal φ10. By supplying the up counter 26, the up counter 26 is initialized (cleared). Reset signal φ1. ．． When is at a low level, the up counter 26 counts the number of pulses of the serial clock φ48C every period until the output of the D-type latch circuit 25 is changed. The exclusive OR circuit 27 detects a mismatch between the input and output of the D-type latch circuit 25, that is, a mismatch between successive bits in the serial input. AND gate 28 outputs serial clock φ1c when exclusive OR circuit 27 detects a mismatch between the input and output of D-type latch circuit 25. The shift register 29 outputs the count value of the up counter 26 in synchronization with the serial clock φ,0 supplied from the AND gate 28. Therefore, the output of the shift register 29 becomes code information of serial data, that is, compressed data.

Since the serial in terminal Sin of the shift register 29 is grounded, each time a shift operation is performed.

Ground level signals will be taken inside.

FIG. 3 shows a block diagram of an example of the decompression circuit 3 for realizing a one-dimensional encoding method.

The decompression circuit 3 will be explained below.

The expansion circuit 3 receives a reset signal φ16. ．． Serial clock φ8G+serial clock φ, 3G, which is obtained by dividing serial clock φ2 by 4, and compressed data are supplied.

The shift register 32 takes in compressed data from the serial in terminal Sin in synchronization with the signal φ! output from the Nant gate 31.
The 9 down counter 33, which is also supplied to the second serial input/output circuit 22, performs a down operation on the data supplied from the shift register 32 in synchronization with the serial clock φ4sc.

The normal data output circuit 34 sends the load signal LOAD to the down counter 33, the signal φ1 and the normal data to the first serial input/output circuit 21, and the signal φ□ to the Nant gate 3.
Output as one input of 1.

FIG. 4 is an example circuit diagram of the normal data output circuit 34. NOR gate 100 inputs the output signal of down counter 33 and forms signal A1.

The output signal of the AND gate 101 inputting the signal A1 and the output signal of the delay circuit D1 is assumed to be B1.

The output signal of the OR gate 102 is set to 01. The output signal C1 of the OR gate 102 is transmitted to the D-type flip-flop 103.
is supplied to the clock terminal CLK of.

The signal output from the D-type flip-flop 1.04 is
This is normal data. In addition, the D-type flip-flop 104
Let the output signal be Dl. The delay circuits Di and D2 are
For example, it is made up of an even number of inverter circuits.

5A to 5F, the mode signal MODEI,
MODE2 indicates a settable operation mode.

5A and 5B show that serial data that is not compressed/expanded can be input/output between the random access memory unit 1 and the outside of the semiconductor storage device 42 of the present invention (hereinafter simply referred to as the outside). 5A.
The operating mode shown in the figure is MODEL=otsuL/to)L
/, MOD E 2 = .

It is set by LOW level, Hyakucho=low level, and DR=high level. The normal data stored in the memory cell array 10 is serially output from the first serial input/output circuit 21 to the outside via the data register, selector 17, and selection circuit 23. The operating modes shown in FIG. 5B are MODEL=low level, MODE2=
The first serial input/output circuit 21 is input from two external sources set by low level, DT=high level, and DR=low level.
The normal data supplied to the memory cell array 10 is an operating mode for writing the normal data to the memory cell array 10 via the selection circuit 23, data register, and selector 17.

When the semiconductor storage device 52 of this embodiment is used as a frame buffer memory for image display, by setting the operation mode shown in FIG. 5A, the first serial input/output circuit 21 can output video signals. Available as a port.

FIGS. 5C and 5D show how the random access memory section 1 operates when compressed data is serially input/output to/from the outside when the random access memory unit 1 is used as a storage area for normal data. That is, the operation mode shown in FIG. 5C is set by MODE1=high level, MODE2=low level, Hyakucho=low level, and DR=high level.

The normal data outputted through the data register and selector 1 selection circuit 23 and the first serial input/output circuit 21 is converted into compressed data by passing through the compression circuit 2, and this data is sent from the second serial input/output circuit 22. This is an operation mode in which serial output is performed externally. The operation mode shown in FIG. 5D is set by MODE1=high level, MODE2=low level, DT=high level, and DR=low level. The compressed data supplied from the outside to the second serial input/output circuit 22 is converted into normal data by passing through the decompression surface JII3, and is then transferred to the first serial input/output circuit 212.
This is the operation mode in which data is written to the memory cell array 10 via the selection circuit 23, data register, and selector 17. When the semiconductor memory device 52 of this embodiment is used as a buffer area for information such as image information for each pixel, By setting the operation mode as shown in FIG. 5C, image information with a large amount of information, such as that obtained by facsimile, can be easily encoded and compressed and transmitted at high speed. On the receiving side, if the operation mode shown in FIG. 5D is set, the received data can be temporarily stored and expanded at the same time.

FIGS. 5E and 5F show how the random access memory section 1 operates when normal data is serially input/output to/from the outside when the random access memory section 1 is used as a storage area for compressed data. That is, the operation mode shown in FIG. 5E is set by MODEL=high level, MODE2=high level, DT=low level, and DR=high level.

The compressed data outputted via the data register and selector 17 selection circuit 23 and the second serial input/output circuit 22 is converted into normal data through the decompression circuit 3, and this is serially outputted to the outside from the f-th serial input/output circuit 21. This is the mode of operation. The operating mode shown in Figure 5F is MODE.
L = high level.

It is set by MODE2=high level, DT=high level, and DR=low level. Normal data supplied from the outside to the first serial input/output circuit 21 is converted into compressed data by passing through the compression circuit 2, and is sent to the memory via the second serial output circuit 222, selection circuit 23, data register and selector 17. This is an operation mode for writing to the cell array 10. By setting the operation modes shown in FIGS. 5E and 5F, the same effect as increasing the storage capacity of the upper memory cell array 10 can be obtained.

FIG. 6 shows an example of an operation timing chart in the operation mode of FIG. 5C.

Before the row address strobe signal RAS changes from high level to low level, when both the data transfer signal 10〒 and the data receive signal 100π go to low level, the controller 5 detects this and determines that it is the serial access mode. The serial access mode means that the random access memory unit 1 inputs and outputs data to and from the outside via the input/output circuit unit 4. data transfer signal
The reset signal φres rises in response to the falling edge of the data receive signal DR. As the data receive signal DR rises, the reset signal φres becomes low level. Here, since the mode signal MODEL is rising and the mode signal MODE2 is falling, the input/output circuit section 4 is transferred from the random access memory section 1 to the input/output circuit section 4.
The compressed data is serially output to the outside via the compression circuit 2. The up counter 26 receives the next serial clock φ411 after the reset signal falls.
The signal supplied from the D-type latch circuit 25 starts counting in synchronization with the falling edge of C, and the signal supplied from the D-type latch circuit 3 starts counting.
When the exclusive OR circuit 27 detects a mismatch between the input and output of the D-type latch circuit 25, which counts again every time the level of the signal supplied from the D-type latch circuit 25 changes, the mismatch detection signal NG becomes high level. . The shift register 29 outputs the result counted by the up counter 26 in synchronization with the falling edge of the serial clock φ8c while the mismatch detection signal NC is at a high level. The signal output from the shift register 29 is supplied as compressed data to the second serial data external terminal via the second serial input/output circuit 22.

The low level normal data for three clocks of the serial clock φ4SG becomes 4-bit binary data for one clock of the serial clock φ4gC by passing through the compression circuit. Further, the high level normal data for 5 clocks of the serial clock φ411G also passes through the compression circuit and becomes 4-bit binary data for 1 clock of the serial clock φ4jC.

In FIG. 6, both the data transfer signal 10〒 and the data receive signal 100π become low level, and then the data transfer signal 10〒, mode signals MODEL, MO
When DE2 becomes high level and the data receive signal DR becomes low level, the operation mode shown in FIG. 5F is entered.

FIG. 7 shows an example of an operation timing chart in the operation mode of FIG. 5D.

After both the data transfer signal 5 lower and the data receive signal 500 become low level, the data transfer signal DR and mode signal MODEL become high level, and the data receive signal DR and mode signal MODE2 become low level, so that the second serial external Terminal. The data supplied to the random access memory section 3 is stored in the random access memory section via the decompression circuit 3.

When the signal A1 becomes low level, the shift register 32 takes in the signal supplied to the serial in terminal Sin as compressed data in synchronization with the serial clock φ,0. The signal B1 becomes low level when the signal A1 becomes low level.

The load signal LOAD becomes low level when the signal A1 and the signal A1 do not match. The signal C1 becomes a clock signal for the D-type flip-flop 104. When the signal D1 is at a high level, the first serial input/output circuit 21 outputs normal data. The 4-bit binary data D○10 corresponding to one clock of the serial clock φ4SC becomes normal data corresponding to two clocks of the serial clock φ4BG by passing through the decompression circuit.

In FIG. 7, the lower level of the data transfer signal 5 is low level, the data receive signal DR, and the mode signal MODE.
When L and MODE2 go high, the operation mode shown in FIG. 5E is entered.

FIGS. 8A and 8B show an example of operation for compressing normal data twice to increase security in transmitting the data. That is, when normal data to be transmitted is transferred from within the system, the normal data is compressed and stored in the random access memory section 1 as shown in FIG. 8A. When transmitting this stored data to another system, the compressed data read from the random access memory unit 1 is compressed once more and sent to the outside as shown in FIG. 8B. FIGS. 9A and 9B show an example of processing on the system side that receives data compressed twice in this manner. That is, as shown in FIG. 9A, upon reception, the received data is decompressed once and temporarily stored in the random access memory section 1. Then, when outputting such data for processing within the system, the data is expanded again as shown in FIG. 9B and then output.

FIG. 10 shows a plurality of compression circuits 2A to 2C and a plurality of decompression circuits 3A to 2C with different compression/decompression processing algorithms.
An example in which 3C is built in in advance will be shown.

The first serial input/output circuit 2 according to system requirements
1. The second serial input/output circuit 22 and a predetermined compression/expansion circuit are connected by the switch means SWI,2. It is assumed that the switch means SWI,2 is controlled by a control signal from the controller 5, for example. In particular, by employing such a configuration, compression/expansion can be performed with high flexibility depending on the applied system, the logic for compression/expansion, and the type of data to be handled.

In the configuration shown in FIG. 10, the first and second serial input/output circuits 21 and 22 may be changed to parallel input/output circuits depending on their compression/expansion logic.

FIG. 11 shows an example block diagram of a compression circuit that is different from the compression circuit of FIG. The compression circuit 4o in FIG. 11 is supplied with a serial clock φ48°, which is obtained by dividing the serial clock φ8Cv serial clock by four, and normal data. Also,
The compression circuit 40 is normally connected to a data input circuit 41. Compressed data output circuit 42. Counter setting circuit 43. shift register 4
4 and an up counter 45.

FIG. 12 is an example circuit diagram of the normal data input circuit 41. Normally, the data input circuit uses two types of serial clocks φsc, φ4 . C9 normal data, 4-bit parallel data Q0 to Q from the up counter 45, and a carry signal CA to notify that when the count exceeds 15 while the up counter 35 is performing a counting operation. The output signal of the D-type flip-flop 110 is
y D A Ta2. The output signal of the D-type flip-flop 111 is delayed DATA 1 and the AND gate 1
The output signal of No. 12 is designated as A2. 114 is normal data and d
This is an exclusive OR circuit that receives two signals of elay DATA2 as inputs. 115 is 1 normal data and delay
This is an exclusive NOR circuit that receives two signals of DATAI as inputs. 116 is a D-type flip-flop whose clock is the output signal of the exclusive NOR circuit 115. AND gate 117 is D-type flip-flop 113, 116
and signal A2 are supplied, and output signal B2 is output to AND gates 119 and 120. or gate 11
8 is a D-type flip-flop 116. Exclusive NOR circuit 1
The three signals of the 15° exclusive OR circuit 114 are supplied, and the output signal plane is connected to the AND gate 119 and the counter setting port J.
Output to li33. The signal output by the AND gate 109 is designated as C2, and the signal C2 is supplied to the shift register 44. Also, the signal output by the AND gate 120 is
Set it to 2. If the signal D2 is at a low level and the signal C2 is at a high level, the shift register 44 takes this signal internally in synchronization with the serial clock φ3° and outputs the signal C2.
2 is at low level, a ground level signal is taken in from the serial in terminal Sin in synchronization with the serial clock φsc.

FIG. 13 is an example circuit diagram of the compressed data output circuit 42. The compressed data output circuit 42 receives a serial clock φ,
8G, 4-bit parallel data Q0 to Q from the up counter 45, and serially shifted data from the shift register 44 are supplied. Nantes Gate 46 is
The output signal is supplied to the counter setting circuit 43. The signal output from the OR gate 47 is compressed data.

FIG. 14 is an example circuit diagram of the counter setting circuit 43. The counter setting circuit 43 has two types of serial clocks φ1lctφ4 . o9 The signal plane and the output signal of the Nant gate 46 of the compressed data output circuit 42 are supplied from the normal data input circuit 41. By these signals, the up counter 45 is initialized (cleared) when the output signal of the AND gate 48 becomes low level.

FIG. 15A shows an operation timing chart of the compression circuit in FIG. 11 when the up-counter 45 counts up 14 normal data signals.
A1 changes with a delay of one clock of the serial clock φsc after the normal data changes because there is also a D-type flip-flop in the preceding stage. Signal NM is supplied to exclusive OR circuit 114 . It changes according to the respective signals supplied from the exclusive NOR circuit 115 and the D-type flip-flop 116. Q0 to Q indicate the count status of the up counter 45. Signal B2 becomes low level if any one of the signals supplied from the AND gate 112° D-type flip-flops 113 and 116 becomes low level. . The signal C2 becomes low level when either the signal πM or the signal B2 becomes low level. The compressed data is output from the compression circuit 4o in synchronization with the serial clock φ8C while the signal D2 is at a low level.

In Figure 15B, 1 normal data is increased to 15 by the up counter.
A description of the previously mentioned signals, which show the operation timing chart of the compression circuit in FIG. 11 when counted, will be omitted.

The carry signal λ falls for a certain period of time when the up counter 45 counts 15. The signal A2 is a carry signal and falls together with A, and rises after a certain period of time after the carry signal CA rises. The compressed data is output from the compression circuit 40 in synchronization with the serial clocks φ and C while the signal D2 is at a low level, as described above.

Figure 15C shows that the normal data is 16 by the up counter.
An operation timing chart of the compression circuit in FIG. 11 when counted is shown.

Similar to FIGS. 15A and 15B, while the signal D2 is at low level,
Compressed data is output from the compression circuit 40 in synchronization with the serial clocks φ and C. Here, 16 cannot be expressed as a 4-bit binary number.

Therefore, first, four consecutive bits of "1" are output to indicate 15. Next, 4 bits of "uO" are output in succession, indicating that there is data following the previously output data of 15. Then, 4-bit binary data with the least significant bit being 1 is output, and 16 is In this way, even if long normal data of the same level is supplied, it can be expressed by connecting several 4-pit binary data.

FIG. 16 shows an example of the configuration of a microcomputer system using the semiconductor memory device of this embodiment. In Figure 16, 50 and 51 are separate microprocessors, and each unit includes at least a main memory, an input/output circuit section/○ for inputting and outputting data with other microprocessors, and a unit for controlling the inside of the microprocessor. It includes 1 CPU. Further, 52 is a semiconductor memory device of this embodiment. At this time, the semiconductor memory device 52 of this embodiment is different from the microprocessor 50 by the first bus means 5.
3 to the random access port, and
A second serial data external terminal is connected to the microprocessor 51 via a second bus means 54. is combined with In this microcomputer system configuration example, the semiconductor storage device 52 of this embodiment has a bus interface function, but since the data transferred to the microprocessor 51 is compressed data, the number of transferred data is reduced. However, the microprocessor 50 and the semiconductor storage device 52
If the data transfer rate between the microprocessor 51 and the semiconductor storage device 52 is the same, the microprocessor 5
Therefore, an empty time is created in the second bus means 54 between the semiconductor memory device 52 and the semiconductor storage device 52. Therefore, the microprocessor 51 uses the vacant second bus means 54 to transfer data with another microprocessor (not shown), thereby improving the overall throughput of the microcomputer system.

FIG. 17 shows another example of the configuration of a microcomputer system using the semiconductor memory device of this embodiment. 1st
In FIG. 7, 55 to 57 are separate microprocessors. In particular, the microprocessors 55 and 56 each include a CPU and the semiconductor memory device 52 of this embodiment, and the operation of the semiconductor memory device 52 is controlled by the CPU. Another microprocessor 57 includes an input/output circuit I10 for inputting and outputting data with other systems, a semiconductor storage device 58 that is different from the semiconductor storage device 52, and a CPU that controls the inside of the microprocessor 57. I'm here. At this time, the microprocessors 55 and 56 are connected via the second serial input/output circuit 22 of the semiconductor storage device 52. In such a configuration, data can be transmitted between both microprocessors 55 and 56 using compressed data, thereby reducing data transmission time. Furthermore, the operating modes shown in FIGS. 8A and 8B and the operating modes shown in FIGS. 9A and 9B are set by the respective CPUs in the semiconductor storage devices 52 included in both microprocessors 55 and 56. In some cases, the data exchanged between the two sides is encrypted, improving the security of the transmitted data.

Although the present invention has been specifically described above based on examples, the present invention is not limited thereto, and can be modified in various ways without departing from the gist thereof. For example, the configurations of the random access memory section and the input/output circuit section, as well as the system configuration to which the semiconductor memory device of the present invention is applied, can be changed as appropriate. Furthermore, the configurations of the compression circuits and expansion circuits or their conversion logic can be changed in various ways.

Furthermore, the method and type of setting of the operating mode in the semiconductor memory device and its contents can be changed as appropriate. For example, each circuit in the input/output circuit section 4 may be made unchangeable after the operation mode is determined according to the user's specifications, or
By managing the address indicating the location where compressed data is stored in the memory array or the address indicating the location where normal data is stored in the memory array, each circuit of the input/output circuit unit 4 is The operating mode of C
Set by PU. Furthermore, the semiconductor memory device of the above embodiment may be used in such a way that only the function of the compression/expansion circuit is used without using the function of the random access memory. That is, for example, according to FIG. 1, data supplied from the first serial data external terminal DjL via the first serial input/output circuit 21 is compressed by the compression circuit 2,
The second serial data is passed through the second serial input/output circuit 22 to the second external terminal. to other systems.

In other words, the compressed data supplied from the second serial data external terminal Dst via the second serial input/output circuit 22 is expanded by the expansion circuit 3, and then directly passed to the first serial data external terminal Ds via the first serial input/output circuit 21. from the plant to another system.

Also, 1st. A selection circuit having a function like the selection circuit 23 may be added so that the external terminals connected to the second serial input/output circuit are common. 5A to 5F, FIG. 8A, FIG. 8B, and FIG. 9A.

Although the compression circuit of FIG. 2 is shown in FIGS. 9B and 10, the compression circuit of FIG. 11 can also be applied.

In the above explanation, the invention made by the present inventor has been mainly applied to a buffer memory for communication data, which is the field of application that formed the background of the invention, but the present invention is not limited thereto, and can be applied to general-purpose storage of data. The present invention can be applied to various semiconductor memory devices such as areas.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

That is, by configuring a semiconductor memory device including an input/output circuit section including a data compression circuit and an expansion circuit connected to at least one port in a random access memory section having a multi-port, and a control means therefor, It is possible to provide continuity between temporary data storage and data compression/decompression processing, allowing high-speed compression/decompression processing of temporarily stored data without putting a burden on the processor or software. It has the effect of being able to

In addition, this device has an operation mode in which data read from the random access memory section is compressed and serially output to the outside, and an operation mode in which data supplied from the outside is expanded and written to the random access memory section. When the random access memory section is used as an area for temporarily storing data before being compressed, the exchange of compressed data between at least one port and the outside can be realized by simple control.

In addition, this device includes an operation mode in which data read from the random access memory unit is expanded and output to the outside, and an operation mode in which data supplied from the outside is compressed and written to the random access memory unit. When the random access memory section is used as an area for temporarily storing compressed data, normal data exchange between at least one port and the outside can be realized by simple control.

Furthermore, by connecting the compression circuit and expansion circuit to the serial access port, it becomes possible to employ a one-dimensional encoding method for data compression/expansion processing.

Furthermore, by making the other ports in the random access memory unit parallel access ports connectable to the data bus, high flexibility can be achieved with respect to system operation or various system requirements.

Furthermore, by making it possible to select an operation mode in which the data read from the serial access port of the random access memory unit is serially output as is, the semiconductor memory device of the present invention can be used as a conventional frame buffer memory for image display or as a video It can also be easily used as RAM, and its uses can be increased.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of a semiconductor memory device according to the present invention. FIG. 2 is a block diagram of an example of a compression circuit, and FIG. 3 is a block diagram of an example of an expansion circuit. FIG. 4 is a circuit diagram of an example of a normal data output circuit, FIGS. 5A to 5F are explanatory diagrams of aspects of some operation modes in the semiconductor memory device of FIG. 1, and FIG. 6 is a timing diagram in the operation mode of FIG. 5C. An example of a chart; FIG. 7 is an example of a timing chart in the operation mode of FIG. 5D; FIGS. 8A and 8B are explanatory diagrams of an example operation mode for improving data security through multiple compression processes. , FIGS. 9A and 9B are explanatory diagrams of m operation modes for improving data security through multiple decompression processes, FIG. 10 is a block diagram showing another example of the input/output circuit section, and FIG. 11 12 is a block diagram of another compression circuit, and FIG. 12 is a circuit diagram of an example of a normal data input circuit. Figure 13 is an example circuit diagram of a compressed data output circuit, Figure 14 is an example circuit diagram of a counter setting circuit, and Figures 15A to 1
FIG. 5C is an operation timing chart of the compression circuit of FIG. 11. FIG. 16 is a block diagram of the configuration of an m system using the semiconductor memory device of FIG. 1, and FIG. 17 is a block diagram of another m system configuration using the semiconductor memory device of FIG. 1. SWI, SW2...switch means, Ilo...input/output circuit, DPOt DPa...parallel data external terminal, Dl...first serial data external terminal, D81...
...Second serial data external terminal, MC...Dynamic memory cell, Yard circuit. SA...Sense amplifier, pc...Prichi Fig. 5A Fig. 5B Fig. 5C Fig. 5D Fig. 5E Fig. 5F Fig. 8A Fig. 8B

Claims (1)

[Claims] 1. Memory means having a plurality of memory cells for storing data; Compression means coupled to the memory means and compressing the supplied data; Coupled with the memory means; A semiconductor memory device in which decompressing means for decompressing supplied data is formed on one semiconductor substrate.