JPH10312355A - Control unit and communication system - Google Patents

Abstract

(57) [Problem] To provide a control unit capable of reading / writing by a DMA method in an arbitrary RAM space without lowering the processing capability of a CPU. SOLUTION: A RAM 1 has two memory blocks 1A,
1B, each memory block 1A, 1B
The CPU 3 can access the two memory blocks 1A and 1B alternately at a predetermined cycle, and can perform the PS conversion. The unit is configured to access the memory block of the two memory blocks 1A and 1B that is not accessed by the CPU 3 at that time at the same cycle as the CPU 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input / output control technique between a peripheral unit and a control unit having a CPU for controlling an entire system such as a facsimile, a printer, and a copying machine.

[0002]

2. Description of the Related Art Conventionally, serial data transfer has been frequently used for exchanging data between a CPU and its peripheral devices in a device such as a copying machine having many I / O devices. The reason is that when parallel data transfer is adopted, the number of wirings (harnesses) to be connected increases, and when the CPU bus is directly connected, the bus line has a high frequency. Is also large. Data serially output from the CPU is converted into parallel data by a serial-parallel conversion element and output to the outside. Parallel input data from the outside is latched by a parallel-serial conversion element, converted into serial data, and sent to the CPU. In the case of data input / output as described above, CP
If data is periodically read out from the RAM area allocated to the U address by the DMA (Direct Memory Access) method, serially converted, and output, the C
When viewed from the PU side, the peripheral elements are convenient because they are equivalent to those assigned to the addresses of the internal RAM of the CPU. However, when reading is performed by the DMA method, the CPU surrenders the bus every time a DMA request occurs, and the operation of the CPU is stopped during that time. Therefore, DMA
If the period is long, it does not matter much, but multiple DM
If factor A exists or if the DMA cycle is short, C
The time for the PU to surrender the bus becomes longer, and the processing efficiency decreases.

In the above case, as shown in FIG.
The problem is somewhat alleviated by separating the storage area of the RAM 1 inside the control unit into two blocks to form the internal memories M1 and M2, for example, using the internal memory M2 as a buffer for serial communication. In this case, as shown in FIG. 11, the address switching unit 4
Is provided. The address switching unit 4 normally selects an address from the CPU 3. When there is an access request from the parallel / serial (PS) conversion unit 2 functioning as the DMA controller, the access is switched to an address for parallel / serial conversion (PS address), and the internal memory is switched from the PS conversion unit 2 to the internal memory. Access M2. At this time, the PS converter 2 issues a wait request signal to the CPU 3 side. However, in this case, the processing efficiency is reduced when the CPU 3 accesses the internal memory M2 which can be accessed by the DMA method.
Since the internal memory M2 is provided as a separate block, RA
Since the buffer area in M1 is fixed, it is difficult to change the buffer capacity, expand the internal memory M1, and the like, and there is a problem of lack of versatility. In addition, in the ordinary synchronous serial data communication, since the transfer data is latched by another signal, there is a problem that the number of harnesses when externally connected is increased. In addition, when the peripheral elements are cascaded, it is inconvenient to perform independent control for each peripheral element. For example, if the number of peripheral I / O devices is three and each bit number is eight, 24-bit data must be transferred and latched even if there is only a one-bit data change. Further, when a plurality of I / O devices are connected in cascade, a trouble of time arbitration occurs particularly when receiving input data. This is because when data is individually transferred from each I / O device to the CPU, data collision may occur on a single transfer line.

[0004]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art.
It is an object of the present invention to provide a control unit capable of reading and writing by a DMA method in an arbitrary RAM space without lowering the processing capability of a CPU. Also,
According to the second aspect of the present invention, in a communication system for performing clock-synchronized serial communication between a control unit including a CPU and a peripheral element via a communication line, the number of harnesses,
An object is to greatly reduce input / output terminals and connectors on the CPU side. According to the third aspect of the present invention,
In addition, even when a plurality of I / O devices are connected in cascade, it is an object of the present invention to prevent data collision at the time of receiving input data and to efficiently perform clock synchronous serial communication.

[0005]

In order to solve the above-mentioned problems, the present invention according to claim 1 comprises a CPU, a RAM and a DMA.
A control unit comprising: a controller;
The AM includes a plurality of memory blocks, each of which is accessible from the CPU,
Data can be read or written by access from the DMA controller, the CPU sequentially accesses the plurality of memory blocks at a predetermined cycle, and the DMA controller In this configuration, a memory block not accessed by the CPU is accessed at the same cycle as the CPU. Further, the invention according to claim 2 is a method according to claim 2,
In a communication system for performing clock synchronous serial communication between a control unit including a U and peripheral elements via a communication line, the communication line transfers a transfer clock signal and transfer data from the CPU side, and The data includes serial data for parallel conversion and command data output to the peripheral element, and the command data includes a command for selecting each peripheral element and a command for controlling each peripheral element. According to a third aspect of the present invention, based on the configuration of the communication system of the second aspect, the serial data output from the CPU side is performed by connecting a plurality of output peripheral elements in parallel or cascade. The serial input to the CPU side is performed by cascading a plurality of input peripheral elements, and each of the input peripheral elements is provided when there is an input data capture request from the CPU side or when input data is received. When the input data changes, the input data is sent to the downstream side as serial data, and the serial data from the upstream peripheral element is stored for a certain period of time. Output transfer data.

[0006]

Embodiments of the present invention will be described below. [Embodiment Corresponding to Claim 1] FIG. 1 is a main part block diagram of a control unit showing an example of an embodiment of the invention described in claim 1. In this embodiment, the storage area of the RAM 1 in the control unit is divided into an upper word RAM block 1A and a lower word RAM block 1B. Further, an upper word address multiplexer 5A and an upper word address multiplexer 5B are provided on the input side of the RAM 1, and the data multiplexers 6A and PS for reading data by the CPU 3 (see FIG. 10) are provided on the downstream side.
A data multiplexer 6B for read data by the conversion unit 2 (see FIG. 10) is provided. Note that, also in this example, the PS converter 2 functions as a DMA controller. In the above case, since one word = 16 bits, the address increases in units of two and is assigned as follows. Address 0 Lower word RAM 2 Upper word RAM 4 Lower word RAM 6 Upper word RAM 8 Lower word RAM ····
When word access is performed, the upper word RAM block 1A and the lower word RAM block 1B are alternately accessed, and one of the blocks 1A or 1B is always accessed.
Is in an unused state (open state). Therefore, if the PS converter 2 performs the DMA in the open state, the D / D conversion is performed without issuing a wait request to the CPU 3 side.
MA can be performed.

That is, in FIG. 1, when the CPU 3 accesses the upper word RAM block 1A, the lower word RAM block 1B is open. When the PS converter 2 determines that there is no access from the CPU 3 at the beginning of the bus cycle, DMA is performed on the block 1A or 1B, and the read data is stored in the P- A line connected to the S conversion unit 2 is selected and read by the multiplexer 6B. FIG. 2 shows the timing when there is a continuous access by the CPU 3 and a repeated DMA request on the PS converter 2 side. By doing so, DMA can be performed without causing a wait state in all RAM areas.
Is performed, and the PS conversion can be performed at a high speed on multiple channels. In the above example, the storage area of the RAM 1 is divided into the upper word RAM block 1A and the lower word RA.
Although the M block 1B is separated into two blocks, it may be further separated into multiple blocks.

FIG. 3 shows an example of a serial data transfer waveform in clock synchronous serial communication. In this example, the transfer data portion has a 9-bit configuration, and the ninth bit is a command bit. When the ninth command bit is 0, the other 8 bits are normal serial transfer data. This data is input to the shift register of the active I / O device, and is latched at the output port by a latch command. FIG. 4 shows the contents of the command data included in the transfer data, and the command data includes a command for selecting and controlling each peripheral element.
In this example, when the command bit is 1, the contents of the second and subsequent lines in FIG. 4 are interpreted as each command. The contents of each command are as follows. The SELECT ALL command is
Activate all connected devices. SE
In the LECT command, only the elements at the addresses specified by A0 to A5 are in the active state, and the other elements are in the non-active state. The BITCLEAR command clears the bits specified by B0 to B2 of the active element. The BITSET command is applied to the B0 of the active element.
The bit specified by .about.B2 is set. The LATCH command latches the contents of the active device shift register. The INPUT REQUEST requests the element side to serially convert the input data to the active element and transmit it to the CPU side. BITCLEAR, BITS above
When the ALL bit is set in each of the ET and LATCH commands, the command applies to all devices regardless of whether it is active or inactive. This makes it possible to send out commands efficiently. With the above command system, when a serial input / output loop is configured as shown in FIG. 5, a plurality of I / O devices (output ports, output ports, Input / output control of the input ports P1 to P3 becomes possible.

FIG. 6 shows the internal configuration of one of the I / O devices, and an individual fixed address is input to each I / O device. As a result of analyzing the input data by the command analysis unit 7, when it is interpreted that the user is selected, the command analysis unit 7 executes the next input / output control command transferred. When it is in the active state, the transfer data is input to the shift register 8 and latched at the output port by a latch command.
When an INPUT REQUEST signal arrives, the data of the input port is loaded into the shift register 8 and output as serial data. As described above, in this embodiment, since the latch is performed by the code of the data portion without using the latch signal, a plurality of I / O devices are provided only by three signal lines of data output, clock, and data input. Input / output control, the number of harnesses, input / output terminals on the CPU side,
Connectors and the like can be greatly reduced.

[Embodiment Corresponding to Claim 3] FIG. 7 is a block diagram of a communication system showing an example of an embodiment of the invention described in claim 3. In this example, the output I / O
O devices (output ports) P11 to P13 are connected in parallel,
Input I / O devices (input ports) P14 to P16 are cascaded. Output I / O devices P11 to P1
3 connected in parallel, the control unit 100
From all I / O devices P11 to P13 in a short time
Is forwarded to In that case, all the output I / O devices P
11 to 13 receive data from the control unit 100, but only the active I / O device executes the received command. Input I / O device P1
Regarding 4 to 16, cascade connection is performed because a plurality of input data collides on a line, which is inconvenient. That is, in this case, the input data is first input to the most upstream I / O device P14, and the downstream I / O devices P15 and P15 are sequentially input.
15 and all I / O devices P14 to P16 for input.
Via the control unit 100. FIG.
1 shows the internal configuration of one of the input I / O devices. In the input I / O device, when there is a change in the input data, the change detection unit 10 detects the change in the input data, and the transfer format generation unit 11 formats the element address, the number of the change bit, and the like. Transfer as serial data. However, since the serial communication lines are cascaded, it is necessary to check whether data of another input I / O device is flowing on the line to avoid data collision.

For this purpose, each input / output device P14
To 16 perform data transfer at the timing shown in FIG.
That is, data from the upstream side is temporarily stored in the shift register 12, and the input data detection device 13 checks whether or not data is coming from the upstream side. As a result, when it is determined that there is no data from the upstream side and there is time to send data for one frame, the transfer data generated by the transfer format generation unit 11 is transmitted to the outside through the multiplexer 14. On the other hand, when there is data from the upstream I / O device, the data stored in the shift register 12 is transferred to the downstream. That is, by providing a time delay of one frame during the transfer from the upstream I / O device to the downstream I / O device, a blank time is found and the own transfer data is inserted. With the above configuration,
Avoid data collision when receiving input data,
The change information of the I / O device on the input side can be sent to the PU3 side. In the above embodiment, the operation in the case where there is a change in the input data has been described. Further, the connection form of the output I / O devices P11 to P13 does not necessarily have to be a parallel connection, but may be a cascade connection like the input I / O devices P14 to P16.

[0012]

As described above, according to the present invention, the following excellent effects can be exhibited. In the control unit according to the first aspect of the present invention, of the plurality of memory blocks in the internal RAM, a memory block not accessed by the CPU at that time is accessed by the DMA method at the same cycle as the CPU. Therefore, it is possible to perform read / write by the DMA method in any RAM space without lowering the processing capability of the CPU. Further, in the communication system according to the second aspect of the present invention, each peripheral element can be selected and controlled by a command included in data transferred from the control unit to each peripheral element. Side input / output terminals, connectors, etc. can be greatly reduced. Further, in the communication system according to the third aspect of the present invention, in addition to the second aspect, even when a plurality of input peripheral devices are cascaded, data collision at the time of receiving input data can be prevented and clock synchronous serial communication can be efficiently performed. It can be carried out.

[Brief description of the drawings]

FIG. 1 is a main part block diagram of a control unit showing one example of an embodiment of the invention described in claim 1;

FIG. 2 is a timing chart showing an example of the embodiment of the invention described in claim 1;

FIG. 3 is a diagram showing an example of a serial data transfer waveform in clock synchronous serial communication according to an embodiment of the present invention.

FIG. 4 is a diagram showing the contents of command data included in transfer data.

FIG. 5 is a block diagram of a communication system showing an example of the embodiment of the invention described in claim 2;

FIG. 6 is a block diagram showing an internal configuration of a peripheral device constituting the communication system of FIG. 5;

FIG. 7 is a block diagram of a communication system showing an example of the embodiment of the invention described in claim 3.

FIG. 8 is a block diagram showing an internal configuration of a peripheral device forming the communication system of FIG. 7;

FIG. 9 is a timing chart showing an example of the embodiment of the invention described in claim 3;

FIG. 10 is a block diagram of a conventional control unit.

FIG. 11 is a block diagram of a main part of a conventional control unit.

[Explanation of symbols]

1 RAM, 1A Upper word RAM block, 1B
Lower word RAM block, 2PS converter, 3C
PU, 5A Upper word address multiplexer, 5B
Upper word address multiplexer, 6A data multiplexer, 6B data multiplexer, 7 command analyzer, 8 shift register, 9 input / output port, 1
0 Change detection unit, 11 Transfer format generation unit, 12
Shift register, 13 input data detection device, 14
Multiplexers, P1 to P3 I / O devices (peripheral elements),
P11 to P13 I / O device (peripheral element), P14 to P
16 I / O device (peripheral element).

Claims (3)

[Claims] 1. A control unit comprising a CPU, a RAM, and a DMA controller, wherein the RAM comprises a plurality of memory blocks, each of which is accessible from the CPU and an access from the DMA controller. Data can be read or written by the
U sequentially accesses the plurality of memory blocks at a predetermined cycle, and the DMA controller determines, among the plurality of memory blocks, a memory block which is not accessed by the CPU at that time at the same cycle as the CPU. A control unit characterized by being accessed by: 2. A communication system for performing clock synchronous serial communication between a control unit including a CPU and a peripheral element via a communication line, wherein the communication line transmits a transfer clock signal and transfer data from the CPU. The transfer data includes serial data for parallel conversion and command data issued to the peripheral element, and the command data includes a command for selecting each peripheral element and a command for controlling each peripheral element. A communication system comprising: 3. The communication system according to claim 2, wherein the output of the serial data from the CPU side is performed by connecting a plurality of peripheral elements for output in parallel or cascade, and the serial input to the CPU side is performed. Is performed by cascading a plurality of input peripheral devices. Each of the input peripheral devices serializes input data when there is an input data fetch request from the CPU side or when input data changes. Sends data to the downstream side, stores serial data from the upstream peripheral device for a certain period of time, and outputs own generated transfer data if no further data comes from the upstream peripheral device during that time. Communication system.