JPH0482840U - - Google Patents

Description

[Brief explanation of drawings]

FIG. 1 is a partially cutaway side view of a vertical wafer support jig according to this embodiment, FIG. 2 is an explanatory diagram showing the positional relationship between the support and wafer according to this embodiment, and FIG.
The figure is an explanatory view showing an example of the use of the vertical wafer support jig according to this embodiment, FIGS. 4 and 5 are side views showing another example of this embodiment with some parts omitted, and FIG. 6 7 is a schematic configuration diagram showing a vertical oxidation diffusion furnace, FIG. 7 is a perspective view partially omitting a vertical wafer support jig according to a conventional example, FIG. 8 is a partially cutaway side view thereof, and FIG. The figure is a partially cutaway side view showing another conventional example. A is a vertical support jig, 1 is a base, 2a and 2b are front columns, 2c and 2d are rear columns, 3 is a wafer, 4 and 5 are grooves, 4a and 5a are the bottom, 4b
and 5b is the top surface, 4c and 5c are wafer mounting surfaces,
B is a wafer transfer jig.

Claims (1)

[Claims for Utility Model Registration] A vertical wafer support jig that places semiconductor wafers in a plurality of wafer support grooves formed in parallel in the vertical direction and supports the wafers in a stacked manner, A wafer characterized in that a portion of the wafer placement surface of the groove farthest from the wafer insertion position is formed lower than a portion of the wafer placement surface near the wafer insertion position. vertical support jig.