JPH042022U - - Google Patents

Info

Publication number
JPH042022U
JPH042022U JP4259390U JP4259390U JPH042022U JP H042022 U JPH042022 U JP H042022U JP 4259390 U JP4259390 U JP 4259390U JP 4259390 U JP4259390 U JP 4259390U JP H042022 U JPH042022 U JP H042022U
Authority
JP
Japan
Prior art keywords
semiconductor
predetermined intervals
manufacturing jig
semiconductor manufacturing
semiconductor wafers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4259390U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP4259390U priority Critical patent/JPH042022U/ja
Publication of JPH042022U publication Critical patent/JPH042022U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Packaging Frangible Articles (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案に係る半導体製造治具の斜視図
、第2図は同じく平面図である。第3図は従来の
半導体製造治具の斜視図、第4図は同じく縦断側
面図である。 5……半導体ウエーハ、5a……底部、5b…
…側部、7……ロツド、9……凹凸部、10……
突起。
FIG. 1 is a perspective view of a semiconductor manufacturing jig according to the present invention, and FIG. 2 is a plan view thereof. FIG. 3 is a perspective view of a conventional semiconductor manufacturing jig, and FIG. 4 is a longitudinal side view of the same. 5... Semiconductor wafer, 5a... Bottom, 5b...
...Side part, 7... Rod, 9... Uneven part, 10...
protrusion.

Claims (1)

【実用新案登録請求の範囲】 多数の半導体ウエーハを、所定間隔で鉛直姿勢
に整列保持する半導体製造治具であつて、 半導体ウエーハの底部及び両側部を支承する3
本のロツドの両端部を連結支持し、前記3本のロ
ツドの半導体ウエーハとの当接面に凹凸部を所定
間隔に形成したことを特徴とする半導体製造治具
[Scope of Claim for Utility Model Registration] A semiconductor manufacturing jig that holds a large number of semiconductor wafers aligned in a vertical position at predetermined intervals, which supports the bottom and both sides of the semiconductor wafers.
1. A semiconductor manufacturing jig, characterized in that both ends of a book rod are connected and supported, and uneven portions are formed at predetermined intervals on the contact surfaces of the three rods with the semiconductor wafer.
JP4259390U 1990-04-20 1990-04-20 Pending JPH042022U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4259390U JPH042022U (en) 1990-04-20 1990-04-20

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4259390U JPH042022U (en) 1990-04-20 1990-04-20

Publications (1)

Publication Number Publication Date
JPH042022U true JPH042022U (en) 1992-01-09

Family

ID=31554271

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4259390U Pending JPH042022U (en) 1990-04-20 1990-04-20

Country Status (1)

Country Link
JP (1) JPH042022U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS647205U (en) * 1987-06-30 1989-01-17

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS647205U (en) * 1987-06-30 1989-01-17

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