JPH0484519A - Phase locked loop circuit - Google Patents

Abstract

PURPOSE:To minimize a phase skip caused when a frequency division clock is selected by comparing a frequency division initializing signal outputted from a 1st frequency divider means selected with a frequency division initializing signal outputted from a 2nd frequency divider means not selected and generating a reset control signal when a phase difference is a prescribed value or over. CONSTITUTION:A reset capacitor 5 compares a frequency division initializing signal outputted from a frequency divider 3 selected as a clock of phase comparison object with a frequency division initializing signal outputted from a frequency divider 4 not selected as the clock of phase comparison object. When a phase difference between a frequency division clock selected as a clock of phase comparison object and a frequency division clock not selected as the clock of phase comparison object reaches a prescribed value, the frequency divider 4 outputting the frequency division clock selected as a clock of phase comparison object is reset. Thus, the phase skip caused when a frequency division clock is selected is minimized.

Description

Detailed Description of the Invention [Industrial Application Field] The present invention relates to a phase synchronization system that corrects the mutual phase difference between divided clock signals generated from a plurality of independent input clock signals and generates a clock for phase comparison. Loop (PLL
: Regarding Phase-Locked Loop) circuits.

[Conventional technology]

Conventionally, in this type of PLL circuit, a plurality of independent input clock signals are input to separate frequency dividers to generate separate frequency-divided clocks, and one of the divided clocks is input to a phase comparator for phase comparison. The clock for the clock is selected in the selector.

[Problem to be solved by the invention]

In a conventional dual prr circuit, when the input clock signal is disconnected and the clocks for phase comparison are switched, there is a large phase difference between the divided clocks divided by the frequency divider. There is a problem that the phase skip increases.

SUMMARY OF THE INVENTION An object of the present invention is to provide a phase-locked loop circuit that can suppress phase skips that occur when frequency-divided clocks are switched.

[Means to solve the problem]

The phase-locked loop circuit of the present invention includes a plurality of first frequency dividing means that frequency divides an input clock signal into a predetermined clock signal and resets an initial frequency division value using a reset control signal; selecting means for selecting one of the divided clocks output from the frequency dividing means as a clock to be subjected to phase comparison; and selecting one of the divided clocks output from the plurality of first frequency dividing means A frequency division initialization signal outputted from the first frequency division means selected by the selection means and a frequency division initialization signal outputted from the first frequency division means not selected by the selection means are compared. reset control signal generation means for generating the reset control signal and outputting it to the unselected first frequency dividing means when the phase difference exceeds a certain value; A phase comparison means for detecting a phase difference with an output clock signal, a low-pass filter for extracting only a low frequency component from the output of the phase comparison means, and an oscillation frequency that is adjusted according to the output of the low-pass filter. This configuration includes a voltage-controlled oscillation means for varying the frequency, and a second frequency-dividing means for frequency-dividing the output of the voltage-controlled oscillation means and outputting the output clock signal.

Further, the phase-locked loop circuit of the present invention has a plurality of first circuits that frequency divides an input clock signal into a predetermined clock signal and resets an initial value of the frequency division by a reset control signal.
a selection means for selecting one of the divided clocks outputted from the plurality of first frequency dividing means as a clock to be phase compared; 11; and a clock selection signal input from the selection signal input terminal; and a frequency division initialization signal output from the first frequency division means selected by the selection means. generating the reset control signal for resetting the first frequency dividing means not selected by the selecting means and outputting it to the first frequency dividing stage not selected by the selecting means; - control signal generation means, phase comparison means for detecting the phase difference between the clock signal selected by the selection means and the output clock signal, and a low frequency component for extracting only the low frequency component from the output of the phase comparison means. a pass filter; a voltage-controlled oscillation means for varying an oscillation frequency according to the output of the low-pass filter; and a second frequency-dividing means for dividing the output of the voltage-controlled oscillation means and outputting the output clock signal. Alternatively, the phase-locked loop circuit of the present invention may include a plurality of first dividers that frequency divide an input clock signal into a predetermined clock signal and reset the initial frequency division value using a reset control signal. a frequency dividing means, a selecting means for selecting one of the divided clocks outputted from the plurality of first frequency dividing means as a clock to be phase compared, and a clock signal selected by the selecting means 117f and an output. a phase comparison means for detecting a phase difference with a clock signal; a low-pass filter for extracting only a low frequency component from the output of the phase comparison means; and an oscillation frequency varying according to the output of the low-pass filter. a voltage-controlled oscillation means for frequency-dividing the output of the voltage-controlled oscillation means to output a +'+if output clock signal, and generating a surface set control signal from the frequency-divided initialization signal; It may also be configured to include second frequency dividing means for outputting to the means.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a configuration diagram showing a first embodiment of the present invention, and
and 2 are clock input terminals, 3 and 4 are first frequency dividers,
5 is a reset I/control unit, 6 is a selector, 7 is a phase comparator,
8 is a low-pass filter, 9 is a voltage controlled oscillator, 10 and 11 are second frequency dividers, ]2 is a clock output terminal, ]3 is a selection signal input terminal r-.

Hereinafter, the operation will be explained using FIG. 1. The input clock signals input from clock input terminals 1 and 2 are the first
is sent to frequency dividers 3 and 4. Normally, the two input clock signals are asynchronous signals, so there is not only a phase shift, but also a phase difference.
Sometimes even the frequencies are different. In the first frequency dividers 3 and 4,
Each human clock signal is frequency-divided by a predetermined value to generate a frequency-divided clock having the same frequency as the clock whose phase is to be compared. At this time, the frequency division initialization signal is simultaneously output to the reset control section 5, and when the reset control signal outputted from the reset control section 5 is received, the first
- Reset the frequency divider from 1 to 1.

The reset control unit 5 inputs the frequency division initialization signals output from the first frequency dividers 3 and 4 and the clock selection signal input from the selection signal input terminal 3, and currently selects the clock as the phase comparison target. The frequency division initialization signal from the first frequency divider that outputs the selected frequency divided clock and the other first frequency divider that outputs the frequency divided clock that is not selected as the phase comparison target clock. The frequency division initialization signal from the frequency divider is compared. Then, if the phase difference between the frequency-divided clock selected as the phase comparison target clock and the frequency division clock not selected as the phase comparison target clock exceeds a certain value, the phase comparison target clock A reset control signal is output for resetting the other first frequency divider outputting a frequency-divided clock that is not selected as a clock. As a result, the frequency-divided clocks that are not selected as phase comparison targets are reset by the reset control signal output from the reset control section 5.

The selector 6 inputs the divided clocks output from the first frequency dividers 3 and 4, and selects the divided clock according to the clock selection signal input from the selection signal input terminal 3. This outputs the output as a phase comparison object. The divided clock that is not selected as the phase comparison target clock is selected as the phase comparison target clock with the frequency divided clock that is selected as the phase comparison target clock by the reset control signal output from the reset I/control unit 5. Since it is reset to 1 when the phase difference with the unselected divided clock exceeds a certain value, the phase difference between both divided clocks is less than a certain value, and the clock selection signal is This means that the phase skip that occurs when a different frequency-divided clock is selected as the phase comparison target clock can be suppressed to a small level.

The phase comparator 7 detects the phase difference between the clock output from the selector 6 and the output clock output from the second frequency divider 1-0, and outputs a DC level proportional to the phase difference. The low-pass filter 8 removes high frequency components included in the DC level output from the phase comparator 7 and outputs it to the voltage controlled oscillator 9. The voltage controlled oscillator 9 has a characteristic of varying the oscillation frequency in proportion to the input voltage, and the oscillation frequency is varied in accordance with the phase difference output from the phase comparator 7 to reduce this phase difference. do the work.

The second frequency divider 10 divides the oscillator output output to the voltage controlled oscillator 9 to a predetermined frequency and outputs it to the phase comparator 7 as an output clock signal. The second frequency divider 1 divides the oscillator output from the voltage controlled oscillator 9 to a predetermined frequency and outputs it as an external output clock.

FIG. 2 is a configuration diagram showing a second embodiment of the present invention.
and 2 are clock input terminals, 3 and 4 are first frequency dividers,
14 is a reset control unit, 6 is a selector, 7 is a phase comparator,
8 is a low-pass filter, 9 is a voltage controlled oscillator, 10 and 11 are second frequency dividers, 12 is a clock output terminal, and 13 is a selection signal input terminal.

The operation will be explained below using FIG. 2. Input clock signals input from clock input terminals 1 and 2 are sent to first-first frequency dividers 3 and 4. Normally, the two input clock signals are asynchronous signals, so not only are they out of phase, but sometimes even in frequency. In the first frequency dividers 3 and 4,
Each input clock signal is frequency-divided by a predetermined value to generate a frequency-divided clock having the same frequency as the clock whose phase is to be compared. At this time, a frequency division initialization signal is simultaneously output to the reset I/control section 5, and when a reset control signal output from the reset control section 5 is received, the first frequency divider is reset.

The control unit 14 inputs the frequency division initialization signals output from the first frequency dividers 3 and 4 and the clock selection signal input from the selection signal input terminal T-13, and currently outputs the phase comparison target. The frequency division initialization signal from the first frequency divider outputting the frequency divided clock selected as the clock of It is output as a reset control signal for resetting the frequency divider of 1 to 1. As a result, clocks that are not selected as phase comparison targets are periodically reset by the reset control signal output from the reset control section 5.

The selector 6 inputs the divided clocks output from the first frequency dividers 3 and 4, and selects the divided clock according to the clock selection signal inputted from the selection signal input terminal 13, thereby selecting a phase comparison target. output as a clock.

The divided clocks that are not selected as phase comparison target clocks are periodically reset by the reset control signal output from the reset control section 5, so the phase difference between the two divided clocks is small. , the phase skip that occurs when the clock selection signal changes and another frequency-divided clock is selected as the clock to be phase compared can be suppressed.

Phase comparator7. Low pass filter 8. Voltage controlled oscillator 9
The operations in the second frequency divider 10, 1.1 are the same as those in the first embodiment described above, and therefore their explanation will be omitted.

In the above-described first and second embodiments, the case where the external input clock signal is powered by two people was explained. Using the division initialization signal from the first frequency divider that outputs the divided clock that is selected as the phase comparison target clock, the divided clock that is not selected as the phase comparison target clock is The basic idea of the present invention can be applied by resetting a plurality of other first frequency dividers outputting .

FIG. 3 is a configuration diagram showing a third embodiment of the present invention, and 1
- and 2 are clock input terminals, ]-5 and 16 are first frequency dividers, 6 is a selector, 7 is a phase comparator, 8 is a low-pass filter, 9 is a voltage controlled oscillator, 11- and 1- 7 is the second
12 is a clock output terminal, and 13 is a selection signal input terminal.

The operation will be explained below using FIG. Input clock signals input from clock input terminals 1 and 2 are sent to first frequency dividers 15 and 16.

Normally, the two input clock signals are asynchronous signals, so not only are they out of phase, but sometimes even in frequency. 1st
The frequency dividers ]-5 and 16 divide each input clock signal by a predetermined value to generate a divided clock having the same frequency as the clock whose phase is to be compared. Also, the first
When the - frequency dividers 15 and 16 receive the reset control signal output from the second frequency divider 17, they reset the first frequency divider. As a result, the frequency-divided clock is periodically reset by the reset control signal output from the second frequency divider]7.

The selector 6 inputs the divided clocks output from the first frequency dividers 15 and 16, and selects the divided clock according to the clock selection signal inputted from the selection signal input terminal 13, thereby selecting a phase comparison target. output as a clock. Since the divided clock is periodically reset by the reset control signal output from the second frequency divider 17, the phase difference between the two divided clocks is small.
This means that the phase skip that occurs when the clock selection signal changes and another frequency-divided clock is selected as the clock to be phase compared can be suppressed.

Phase comparator7. Low pass filter 8. Voltage controlled oscillator 9
and the second frequency divider 1] are the same as those in the first embodiment described above, so a description thereof will be omitted.

The second frequency divider 17 divides the oscillator output output from the voltage controlled oscillator 9 to a predetermined frequency and outputs it to the phase comparator 7, and also generates a reset control signal from the frequency division initialization signal, Output to the first frequency divider 15.16.

In the third embodiment described above, the external human clock signal is
Although the explanation has been given by taking up the case of manual power, even if the external human power clock signal is 3 or more human power, multiple frequency divided clocks are output by the reset I/control signal output from the second frequency divider 1-7. The basic idea of the invention can be applied by resetting the other first frequency divider.

〔Effect of the invention〕

As described above, in the present invention, the reset control means outputs the divided initialization signal from the first frequency dividing means outputting the divided clock selected as the phase comparison target clock, and the phase The frequency division initialization signal from the first frequency dividing means outputting the frequency division clock that is not selected as the clock to be compared is compared, and the phase of the frequency division clock that is selected as the clock to be compared is determined. If the phase difference with the divided clock that has not been selected as the clock to be compared exceeds a certain value, the first clock that is outputting the divided clock that has not been selected as the clock to be phase compared
or the initial frequency division from the first frequency dividing means outputting the divided clock selected as the phase comparison target clock by the reset control means. The first frequency dividing means, which outputs a divided clock that is not selected as a clock to be phase compared, is periodically reset using the oscillation signal, or the output of the voltage controlled oscillation means Using the frequency division initialization signal of the second frequency division means which divides the frequency and outputs it to the phase comparison means, the first frequency division means which outputs the input frequency division clock to the selection means is periodically controlled. By configuring to reset the frequency division clock, it is possible to suppress the phase skip that occurs when the frequency division clock is switched, and it is possible to suppress the phase skip that occurs when the frequency division clock is switched.

[Brief explanation of drawings]

Figure 1 is a configuration diagram showing a first embodiment of the invention, Figure 2 is a configuration diagram showing a second embodiment of the invention, and Figure 3 is a configuration diagram showing a third embodiment of the invention. It is a diagram. 1.2... Clock input terminal, 3, 4, 10° 1-1. , 1.5. 1.6. 1.7・・・・・・
Frequency divider, 5, 14... Reset control section, 6...
... Selector, 7 ... Phase comparator, 8 ...
...Low pass filter, 9...Voltage controlled oscillator, 12...Clock output terminal, 1-3...
...Selection signal input terminal.

Claims (1)

[Scope of Claims] 1. A plurality of first frequency dividing means for dividing an input clock signal into a predetermined clock signal and resetting an initial value of the frequency division by a reset control signal; selection means for selecting one of the divided clocks outputted from the frequency dividing means as a clock to be phase compared; and selecting the divided initialization signal from among the divided initialization signals outputted from the plurality of first frequency dividing means. Comparing the frequency division initialization signal output from the first frequency division means selected by the means with the frequency division initialization signal output from the first frequency division means not selected by the selection means. reset control signal generating means for generating the reset control signal and outputting it to the unselected first frequency dividing means when the phase difference exceeds a certain value; phase comparison means for detecting a phase difference between the clock signal and the output clock signal;
a low-pass filter for extracting only low frequency components from the output of the phase comparison means; voltage-controlled oscillation means for varying the oscillation frequency according to the output of the low-pass filter; and an output of the voltage-controlled oscillation means. and second frequency dividing means for dividing the frequency of the clock signal and outputting the output clock signal. 2. A plurality of first frequency dividing means for frequency dividing an input clock signal into a predetermined clock signal and resetting an initial value of the frequency division by a reset control signal; selection means for selecting one of the frequency-divided clocks as a phase comparison target clock; and a frequency-divided initialization signal output from the plurality of first frequency division means and a clock input from the selection signal input terminal. a selection signal, and resets the first frequency dividing means not selected by the selecting means using a frequency dividing initialization signal output from the first frequency dividing means selected by the selecting means. a reset control signal generating means for generating the reset control signal for the first frequency dividing means and outputting it to the unselected first frequency dividing means; and detecting a phase difference between the clock signal selected by the selecting means and the output clock signal. a phase comparison means; a low-pass filter for extracting only low frequency components from the output of the phase comparison means; a voltage-controlled oscillation means for varying an oscillation frequency according to the output of the low-pass filter; and second frequency dividing means for frequency dividing the output of the controlled oscillation means and outputting the output clock signal. 3. A plurality of first frequency dividing means for frequency dividing an input clock signal into a predetermined clock signal and resetting an initial value of the frequency division by a reset control signal; selecting means for selecting one of the frequency-divided clocks as a clock to be subjected to phase comparison; phase comparing means for detecting a phase difference between the clock signal selected by the selecting means and the output clock signal; a low-pass filter for extracting only low frequency components from the output of the means; voltage-controlled oscillation means for varying the oscillation frequency according to the output of the low-pass filter; and frequency-dividing the output of the voltage-controlled oscillation means. and second frequency dividing means that outputs the output clock signal, generates the reset control signal from the frequency division initialization signal, and outputs it to the first frequency dividing means. circuit.