JPH0485838A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To prevent deterioration of characteristics of integrated circuit, e.g. increase of delay time, by making bores through a bonding pad and decreasing the actual area of the bonding pad thereby decreasing the capacitance between the bonding pad and a semiconductor substrate. CONSTITUTION:At first, individual elements 5 and an insulating film 6 are formed followed by formation of an aluminum fib 12. Aluminum wirings 3, 4 and bonding pads 10, 11 having multiple bores are then fanned simultaneously by the use of a photomask 13. Lead wires 8, 9, e.g. gold wires, are finally bonded to the bonding pads 10, 11 having bores thus producing a semiconductor integrated circuit. According to the constitution, capacitance between the bonding pad and the semiconductor substrate is decreased resulting in prevention of deterioration of characteristic due to stray capacitance.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor integrated circuit.

[Conventional technology]

Conventionally, in semiconductor integrated circuits, wiring formed by patterning a thin aluminum film has been used to realize electrical connections between the individual elements constituting the circuit. In order to take out the electrical connection from the end of the aluminum wiring to the outside, it is common practice to enlarge the area of the end of the aluminum wiring to form a bonding pad, and to weld a lead wire such as a gold wire to this part. It's been coming. FIG. 8 is a plan view of a conventional semiconductor integrated circuit, and FIG. 9 is a cross-sectional view taken along line AA shown in FIG. In the figure, (1) and (2) are bonding pads, (3) and (4) are aluminum wiring, (5) are individual elements, (6) are insulating films, (7) are semiconductor substrates, and (8) are ,
(9) is a lead wire.

Next, the operation will be explained.

In the integrated circuit shown in FIG.
), When the size of (2) is 150μ square and the insulating film (6) is a silicon oxide film with a film thickness of 1μ, the capacitance between the bonding pads (1), (2) and the semiconductor substrate (7) is becomes a maximum of 5.2×10 PF.

[Problem to be Solved by the Invention 1] Since the conventional semiconductor integrated circuit is configured as described above, the capacitance between the bonding pad and the semiconductor substrate acts as a stray capacitance, causing problems such as increasing delay time. There were problems such as deterioration of the characteristics of the integrated circuit.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to obtain a semiconductor integrated circuit with improved characteristics by reducing the actual area of bonding pads.

[Means for Solving the Problems] A semiconductor integrated circuit according to the present invention has a bonding pad provided with a large number of openings.

[Effect]

The semiconductor integrated circuit according to the present invention has many openings in the bonding pad to reduce the actual area.
The electrostatic capacitance between the bonding pad and the semiconductor substrate is reduced to prevent deterioration of the characteristics of the semiconductor integrated circuit due to stray capacitance.
The figure is a plan view of a semiconductor integrated circuit, and Figure 2 is a B shown in Figure 1.
3 to 5 are sectional views shown according to the manufacturing process of the semiconductor integrated circuit shown in FIG. 1, and FIG.
'i A plan view showing a photomask for forming a bonding pad provided with the opening shown in FIG. 1, and FIG. FIG. 3 is a plan view of a bonding pad provided with an opening, showing a case where the number of holes is increased. In the figure, (1) to (9) are the same as those shown in the conventional example of FIGS. 8 and 9, and therefore their explanation will be omitted. (10), (11), (15
) is a bonding pad with an opening, (12) is a Marumi film (13) is a photomask, (14) is an opening, (
16) is a lead wire.

Next, the operation will be explained. First, the manufacturing method will be explained with reference to FIGS. 3 to 6. As shown in Figure 3,
Individual elements (5) and an insulating film (6) (silicon oxide film, 1 μm thick) are formed. Next, as shown in FIG. 4, a layer of aluminum #12 (1μ) is formed. Then, using a photomask (13) shown in FIG. 6, by a known photolithography technique,
Aluminum wiring (3L (4)) and bonding pads (10) and (11) having a large number of openings are formed simultaneously as shown in FIG. 5.Finally, bonding pads (10) with openings, (11) Lead wire such as gold wire (
By welding 8) and (9), the semiconductor integrated circuit shown in FIG. 1 is obtained.

A bonding pad (10
), (11) As shown in FIG. 7, when a bonding pad (15) having a 150μ square opening with twelve 25μ square openings (14) is used, this and the semiconductor The capacitance between the substrates (7) is up to 3.5
The stray capacitance is reduced to 10 to 3 pF, and the characteristics of the semiconductor integrated circuit are improved.

Incidentally, in the above embodiment, the case where the shape of the openings (14) of the bonding pads (10), (11), and (15) having openings is square was explained. Needless to say, the same effect can be obtained regardless of the shape.

[Effects of the Invention] As described above, the present invention has the effect of reducing the capacitance between the bonding pad and the semiconductor substrate by providing a bonding pad with an opening, thereby preventing deterioration of characteristics due to stray capacitance. There is.

[Brief explanation of the drawing]

FIG. 1 is a plan view of a semiconductor integrated circuit according to an embodiment of the present invention, FIG. Lj1g2 is a sectional view taken along line BB shown in FIG. 1, and FIGS. 6 is a plan view showing a photomask for forming a bonding pad provided with the opening shown in FIG. 1, and FIG. 7 is a cross-sectional view shown according to the process. FIG. 8 is a plan view of a bonding pad provided with openings showing a case where the number of openings in the bonding pad is increased; FIG.
The figure is a plan view of a conventional semiconductor integrated circuit, and FIG. 9 is a cross-sectional view taken along line AA shown in FIG. In the figure, (31, (4+) is aluminum wiring, (5) is element, (6) is insulating film, (7) is semiconductor substrate, (8),
(9), (16) are lead wires, (10), (11)
), (15) is a bonding pad with an opening,
(12) is an aluminum film, (13) is a photomare film, (14)
) is the opening. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] A semiconductor integrated circuit characterized by reducing the capacitance between the bonding pad and the semiconductor substrate by providing an opening in the bonding pad to reduce the actual area of the bonding pad, thereby preventing deterioration of characteristics due to stray capacitance. circuit.