JPH0485872A - Semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor devices, and in particular to A semiconductor devices in which transistors are arranged in an orderly manner to form a circuit using a CMOS process.
It relates to semiconductor devices such as SIC, SOG, and semi-custom IC.

[Conventional technology]

With conventional technology, to configure a CMOS transistor,
This method places the P-channel region and N-channel region of the transistor on the same plane.

The source, drain, and gate were placed on the same plane, so at the transistor level, it was about 2@
This means that it would have required a floor area of .

[The invention aims to solve all problems.However, in the conventional technology, the transistors (P-channel side transistor, N-channel transistor) mounted on one chip were arranged on the same plane, so at the transistor level, the problem was approximately doubled. This will require a floor area of
In the world of semi-custom ICs such as ASIC and SOG, where the number of transistors mounted is increasing, the only way to increase the number of gates mounted is to increase the area of the IC chip. Therefore, the present invention proposes a Pch side transistor and an N
By configuring the chl-transistors in the vertical direction, the area covered by the transistors can be effectively reduced to 172, so that the above problem can be solved.

[Means to solve the problem]

The semiconductor device of the present invention is characterized in that the area of the CMOS transistors can be reduced to about 1/2 by vertically stacking the Pch side transistors and the Nchh transistors in the arrangement of the transistors.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the arrangement layout of CMOS transistors in a conventional semiconductor device using an inverter circuit as an example.

In the figure, 101 is the Pch II power supply source, which is usually VDD.
This is aluminum wiring. 102 in Figure 0, which is the source part of the Pchh transistor, is a polysilicon wiring.
03 is a field region that constitutes a PCh transistor. In the figure, 104 is the drain portion of the PcH transistor region.

In order to connect the field 103 and the aluminum wiring 105, a hole called a contact is opened to provide electrical continuity.

In the figure, reference numeral 105 is an aluminum wiring for connecting the drain portions of the Pch and Nch of this transistor and for transmitting output signals and the like. In the figure, 106 is the drain portion of the NCHCM transistor. Field 107 and aluminum wiring 105
107 in the figure is a field part that constitutes an Nch side transistor. 108 in the figure is a GND level power supply source. 109 is the gate portion of the Pchl-transistor; 110 in the figure is the gate portion of the Nch transistor.

A CMOS transistor is made with the above configuration.

FIG. 2 is a sectional view of the CMOS IC of the present invention.

In the figure, 201 is a contact that connects Pch and Nch. Referring to FIG. 1, this refers to areas 104, 105, and 106. In the figure, 202 is the source or drain portion of the Pch transistor.

The same goes for 204, if 202 sets the source, 204
is the drain, and if 202 is set as the drain, 204
can be set for each source.

203 in the figure is the gate part of the Pch-transistor 0 205 in the figure is a contact for connecting the source or drain signal to the aluminum wiring 0 206 in the figure constitutes the source or drain region of the Nch side transistor The field portion 207 in FIG. 0 is the gate portion of the Nch transistor.

In the figure, 208 is the source or drain portion of the Nch side transistor. When 206 is set as a source, 208 is set as a drain, and when 206 is set as a drain, 208 is set as a source.

〔Effect of the invention〕

As described above, the present invention has the structure of the transistor as Pc.
By configuring the h region and the Nch region in the vertical direction, the area of the conventional transistor can be reduced to about 1/2. This makes it possible to mount twice as many transistors on an IC with the same area as before.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram when a Pch region and an Nch region of a CMOS transistor, which is a semiconductor device of the present invention, are vertically stacked. FIG. 2 is a cross-sectional view of CMo5zc of the present invention. 101...VDD or vSS line 102...
・Transistor gate part 103...Pch drain part 104...Pch drain part output output contact 10
5. Drain output section 106... Nch drain section output output contact 10
7.Nch transistor source section 108...■SS
, or VDD line 109...Pch) transistor gate part 110...Nch l- transistor gate part 201...Pch+Nch connection contact 202...PCh transistor source part 203...
...Pch transistor gate section 204...Pch
Transistor drain part 205...Pch, Nch connection contact 206...Pch L-transistor source part 207...Pch) Transistor gate part 208...
・・Pch transistor drain part number top

Claims (1)

[Claims] A semiconductor device characterized in that it is configured by vertically stacking a P channel region and an N channel region of a CMOS transistor.