JPH0485884A - Manufacturing method of semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a technique that is effective when applied to a method of manufacturing a PN junction diode formed in a silicon thin film.

(Prior Art) A conventional method for manufacturing a PN junction diode formed in a silicon thin film uses a resist mask to form a P shadow region or an N shadow region.

FIGS. 2(a) to 2(e) are main sectional views of a manufacturing method according to the prior art. The following will be explained in order. In all sections of the conventional example, those having the same function are given the same reference numerals, and repeated explanation thereof will be omitted.

First, as shown in FIG. 2(a), a first
Approximately 3,000 people will form the insulation 111202. Thermal oxidation method or CVD method (chemical vapor deposition method) in an oxygen atmosphere
It would be appropriate to form SiOx 11I or the like using the CVD method.
Approximately 00 people will be formed. A polycrystalline silicon film deposited by thermally decomposing monosilane gas at a temperature of around 620° C. would be suitable, and in order to form the N shadow region 208, a group V element (for example, phosphorus or arsenic) is added. Normally, the ion implantation method is used. The amount of DO3E is 1xlO
Approximately "atoms-cm-" would be appropriate.

Next, as shown in FIG. 2(b), unnecessary portions of the silicon g203 are removed by ordinary photo-etching methods.

Next, as shown in FIG. 2C, a resist mask 205 is formed in the area other than the P-type region 209, and a group III element (for example, boron) is implanted using the normal ion implantation method described above. DOS greater than DO5E amount of group V elements
The amount of E, that is, approximately 1×10"atoms-cm-" is implanted. As a result, the N shadow area 208 is canceled and becomes a P shadow area 209.

Next, as shown in FIG. 2(d), the resist mask 205 is removed and a second insulating film 207 is formed! , CVD method, Sz Oz III wo 2000 A is formed.

Then, heat treatment is performed to activate the V iron impurity element and the Group III Inl element. Annealing is performed at 1100° C. for 1 minute in a nitrogen atmosphere using a halogen lamp. Then, by photo-etching, the second area on the N shadow area 208 and the P shadow area 209 is etched.
A contact hole 210 is formed in the insulating film 207.

Next, as shown in FIG. 2(e), aluminum is formed as a wiring 211 on the second insulating film 207 and the contact hole 210 by sputtering, and unnecessary portions are removed by photo and etching.

A PN junction diode was formed in the silicon film through the above-described conventional steps.

[Problems to be Solved by the Invention] However, the conventional technology has a problem in that miniaturization is not possible. Normally, mechanical misalignment occurs during the photo process, so an extra portion called "alignment margin" is required.

In the conventional technology, three alignment allowances are required: an alignment allowance between the silicon film 203 and the resist mask 205, an alignment allowance between the P shadow region and the contact hole 210, and an alignment allowance between the contact hole 201 and the line 11211. Miniaturization was marginalized.

SUMMARY OF THE INVENTION The present invention aims to solve these problems, and its purpose is to provide a thin silicon IPN junction diode that can be miniaturized with little margin for alignment.

[Means for Solving the Problems] A method for manufacturing a semiconductor device of the present invention includes: (1) forming a first insulating film on a semiconductor substrate; and forming a silicon film on the first insulating film. , a step of implanting a first impurity of the Nl group or V group into the silicon film, a step of forming a second insulating film on the silicon film, a step of forming a contact hole in the second insulating film, and a step of forming a contact hole in the second insulating film. The method is characterized by comprising a step of implanting a second impurity of a group different from the first impurity into the silicon film, and a step of forming a wiring layer over the contact hole.

Embodiment 1 FIGS. 111(a) to 1(e) are main cross-sectional views of a method for manufacturing a semiconductor device according to an embodiment of the present invention. In addition, in all the figures of the embodiment, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

The following is an explanation based on FIGS. 1(a) to 1(e).

First, as shown in FIG. 1(a), a first
The insulating film 202 is formed by about 3,000 people. r! ! ! Basic,
It would be appropriate to form the 5102 film or the like by thermal oxidation or CVD (chemical vapor deposition) in an atmosphere. Then, a silicon film 103 is formed by approximately 5,000 people using the CVD method. A polycrystalline silicon film deposited by thermally decomposing monosilane gas at a temperature of around 620° C. may be suitable.
A typical ion implantation method is used to implant elements of the group 6, such as phosphorous and arsenic. The amount of DOSE is I
toms-cm-'' would be appropriate.

Next, as shown in FIG. 1(b), unnecessary portions of the silicon film 103 are removed by ordinary photo and etching methods, and a second insulating film 1 is formed on the silicon film 103.
05 is formed to a thickness of 5000 Å or more. 510 by CVD method
A two-layer film would be appropriate.

Next, as shown in FIG. 1(c), a first contact hole 107 is formed on the portion where the P shadow region 106 is to be formed.
The first contact hole 107 is formed therein. Then, after removing the resist mask of the photo-etching method, a group III element (for example, boron) is implanted to form a P shadow region. Using an ion implantation method, an amount of DO5E is implanted that is larger than the amount of DO5E of the group V element, that is, about 1 x l O"atoms-cm"'. As a result, the N shadow areas 104 are canceled and the P
It becomes a shadow area. Note that since the second insulating film 105 functions as a mask, the DI group element is not implanted into the N shadow region 104 other than the first contact hole 107.

Next, as shown in FIG. 1(d), the wiring 1 is placed in the N shadow area 104.
In order to connect 10, a second contact hole 111 is formed by a conventional photo-etching method. Then, heat treatment is performed to activate the group V impurity element and the group III impurity element. Annealing is performed at 1100° C. for 1 minute in a nitrogen atmosphere using a halogen lamp.

Next, as shown in FIG. 1(e), the first contact hole 1
07 and the wiring 110 in the second contact hole 111.
Aluminum is formed by sputtering, and unnecessary parts are removed by photo-etching.

Through the process according to the technology of the present invention described above, P is added to the silicon film.
An N-junction diode is formed.

In this way, by substituting the second insulating film 105 for the ion implantation mask for forming the P shadow region, the P shadow region 106 and the first contact hole 10
7 coincide with each other, no alignment margin is required and miniaturization becomes possible accordingly. Moreover, despite this effect, the Beni divisor has not increased.

Although the invention made by the present inventor has been specifically explained based on the above embodiments, the present invention is not limited to the above embodiments, and can be modified in various ways without departing from the gist thereof. Of course you can get it.

For example, it is possible to add group III and group V impurities.

For example, in this embodiment, after removing the photoresist for forming the first contact hole,
Alternatively, a photoresist for forming the first contact hole 107 is formed, the first contact hole 107 is etched, and immediately after that, the group III impurity ion is implanted. A similar effect can be obtained even if the photoresist is removed. In that case, the second insulation 111105
The film thickness of can be made thinner.

[Effects of the Invention 1] As described above, according to the method for manufacturing a semiconductor device of the present invention, by implanting P-type impurities through the contact hole for wiring, the alignment margin between the contact hole and the P-type impurity region can be improved. is no longer necessary, and it becomes possible to produce a miniaturized silicon thin film PN junction diode.

[Brief explanation of the drawing]

FIGS. 1(a) to 1(e) are main sectional views showing an embodiment of the method for manufacturing a semiconductor device of the present invention. FIGS. 2(a) to 2(e) are main cross-sectional views showing an example of a conventional method for manufacturing a semiconductor device. - Semiconductor substrate - First insulating film - Silicon film - N shadow region - Second insulating film - P shadow region - First contact hole - V group impurity ion beam - III group impurity ion beam 110 ・ 111 ・ 201 ・ 202 ・203 ・ 204 ・ 205 ・ 206 ・ 207 ・ 208 ・ 209 ・ 210 ・ 211 ・ ・Wiring・Second contact hole・Semiconductor substrate・First! E-edge film, silicon film, group V impurity ion beam, resist mask, group II impurity ion beam, second insulating film, N shadow region, P shadow region, contact hole, etc. Wiring Applicant Seiko Epson Corporation Agent Patent attorney Master Suzuki Kisanbe (and 1 other person) To108 (arrow) (shi) (廄) (ma)

Claims (1)

[Claims] (1) A step of forming a first insulating film on a semiconductor substrate, a step of forming a silicon film on the first insulating film, and a step of implanting a group III or group V first impurity into the silicon film. , forming a second insulating film on the silicon film, forming a contact hole in the second insulating film, and implanting a second impurity of a different group from the first impurity into the silicon film. . A method of manufacturing a semiconductor device, comprising the steps of forming a wiring layer on the contact hole.