JPH0485935U - - Google Patents
Info
- Publication number
- JPH0485935U JPH0485935U JP12843890U JP12843890U JPH0485935U JP H0485935 U JPH0485935 U JP H0485935U JP 12843890 U JP12843890 U JP 12843890U JP 12843890 U JP12843890 U JP 12843890U JP H0485935 U JPH0485935 U JP H0485935U
- Authority
- JP
- Japan
- Prior art keywords
- digital
- signal
- analog
- converter
- bit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000003111 delayed effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
Description
第１図はこの考案の一実施例による遅延検波器
を示す図、第２図は従来の遅延検波器を示す図で
ある。図において１はアナログ・デイジタル変換
器、２はシフトレジスタ、３はデイジタル・アナ
ログ変換器、４は乗算器、５は低域ろ波器、６は
クロツク発生器、７は入力ＰＳＫ波、８は復調出
力である。なお、図中、同一符号は同一、または
相等部分を示す。
FIG. 1 is a diagram showing a delay detector according to an embodiment of this invention, and FIG. 2 is a diagram showing a conventional delay detector. In the figure, 1 is an analog-to-digital converter, 2 is a shift register, 3 is a digital-to-analog converter, 4 is a multiplier, 5 is a low-pass filter, 6 is a clock generator, 7 is an input PSK wave, and 8 is a This is the demodulated output. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
ル信号に変換するアナログデイジタル変換器と、
前記デイジタル信号をＰビツト遅延させるｎビツ
ト並列のシフトレジスタと、前記Ｐビツト遅延さ
れたｎビツトデイジタル信号をアナログ信号に変
換するデイジタルアナログ変換器と、入力アナロ
グ信号とデイジタルアナログ変換器の出力信号と
を乗算する乗算器とこの乗算器の出力信号の低域
成分を検波出力信号として出力する低域ろ波器と
、前記アナログ・デイジタル変換器、シフトレジ
スタおよびデイジタルアナログ変換器とを駆動す
るクロツク発生器とから成ることを特徴とする遅
延検波器。 an analog-digital converter that converts an input analog signal into an n-bit digital signal;
an n-bit parallel shift register for delaying the digital signal by P bits; a digital-to-analog converter for converting the n-bit digital signal delayed by P bits to an analog signal; and an input analog signal and an output signal of the digital-to-analog converter. a multiplier for multiplying by A delay detector comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12843890U JPH0485935U (en) | 1990-11-30 | 1990-11-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12843890U JPH0485935U (en) | 1990-11-30 | 1990-11-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0485935U true JPH0485935U (en) | 1992-07-27 |
Family
ID=31875899
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12843890U Pending JPH0485935U (en) | 1990-11-30 | 1990-11-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0485935U (en) |
-
1990
- 1990-11-30 JP JP12843890U patent/JPH0485935U/ja active Pending
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