JPH0487360A - Hybrid integrated circuit device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a hybrid integrated circuit device, and more particularly to a wiring connection structure for a hybrid integrated circuit device equipped with a memory and a microcomputer.

(0) Conventional technology A conventional hybrid integrated circuit device will be explained with reference to FIG.

FIG. 4 shows a plan view of a hybrid integrated circuit device, which includes an insulated metal substrate (70), a conductive path (72),
A relay pad (74), an external lead pad (76), a bonding wire (78), and a first gate array (
80), microcomputer (82), memory (84)
), a second gate array (86), other peripheral integrated circuits (88), and a chip resistor (9).
0) etc.

The insulated metal substrate (70) is mainly an insulated aluminum substrate, and a wiring pattern is formed in a predetermined shape by photo-etching a copper foil adhered to the insulated metal substrate (70), and then integrated as described below. Pads for fixing circuit elements, pads for connecting their electrodes, conductive paths (72) such as relay pads (74), pads for external leads (76), etc. are formed.

At predetermined positions of the conductive path (72), there are first and second gate arrays (80) (86), a microcomputer (82), a memory (84), and a peripheral integrated circuit (86).
The chip-shaped elements forming 8) are fixed with an Ag base, and electronic components such as chip capacitors and chip resistance elements are fixed with solder taking connection strength and contact resistance into consideration.

Such large-scale hybrid integrated circuit devices are used in a wide variety of electrical equipment, and in recent years have also been used as printer controllers.

To briefly explain the case where a general printer controller is realized as a hybrid integrated circuit device, for example, the first gate array (80) is connected manually to the Centronics specification parallel data, sensor input, printer front panel switch signals, etc. microcomputer (8
2), and the second gate array (86) functions as a human power interface for the microcomputer (86).
It functions as an output interface that outputs a character font to the print head based on the command 2), and also outputs control signals such as a carriage return or feed forward signal. Further, the microcomputer (82) is, for example, an 80-pin microcomputer with a 16-bit human output and a 20-bit address space, and the memory (84) is, for example, a 256-bit, 28-bin memory. be done.

The hybrid integrated circuit device having the above structure can meet the demand for miniaturization required for printer controllers, and also solves the problem of heat dissipation from the device since it uses an insulated metal substrate.

(c) Problems to be Solved by the Invention However, the wiring pattern of a large-scale digital circuit that has a 16-bit data bus and a 20-bit address space has become extremely complex. Conductive paths such as
They had to be interconnected using a technique called jumping wire connections.

By using such jumping wire connection technology,
Although connections can be made between relatively distant conductive paths, hybrid integrated circuit devices equipped with microcomputers, memories, etc. that require an extremely large number of data buses and address buses, as shown in Figure 4, require an extremely large number of data buses and address buses. Jumping wire was needed. As a result, the effective board mounting area decreased due to the increased number of pads for fixing the jumping wires, and there were limits to miniaturization of the device, making it difficult to realize a large-capacity, ultra-small hybrid integrated circuit device. .

In addition, since many buses are arranged around the integrated circuit device, which is composed of as many as 80 bins, connecting all the electrodes to the required buses requires multiple wiring connections. .

(d) Means for Solving the Problems The present invention has been made in view of the above problems, and is a method of forming wiring patterns and bonding pads for address buses, data buses, etc. around elements such as memory and microcomputers. By arranging the multilayer board insulated and connecting predetermined conductive paths to each other and connecting the electrodes of the microcomputer and the electrodes of its peripheral circuit elements, etc., the number of wire bonding is significantly reduced and high reliability is achieved. Furthermore, the present invention provides a high-density and small-sized hybrid integrated circuit device.

(e) Since the address bus, data bus, etc. are connected via conductive paths formed on the functional multilayer board, long-span connections are possible, and connections between the microcomputer and its peripheral circuit elements, as well as the microcomputer Further, in connection between peripheral circuit elements and a predetermined conductive path, it is possible to eliminate the need for conventional dipping wire connections.

Further, adjacent to elements such as memory and microcomputers, pads to be bonded to their electrodes and buses connected thereto are arranged in multiple layers, so that connection to a predetermined bus can be made at the shortest possible distance.

(F) Embodiment Hereinafter, an embodiment in which the present invention is applied to a hybrid integrated circuit device for a printer controller will be described with reference to FIGS. 1 to 3.

FIG. 1 is a plan view of the embodiment, and the hybrid integrated circuit device has an insulating metal substrate (12) (however, the plan view only shows the insulating resin layer formed on the metal substrate). , when explaining the cross-sectional structure below, an insulated metal substrate (
12) (the reference number 12) is also used for the insulating resin layer), a conductive path (14) formed in a predetermined pattern on this insulating metal substrate (12), a buffed external lead (18), and a first gate array. (24), micro combi coater (26),
A memory (28), a second gate array (30), other peripheral integrated circuits (32), a chip resistor (34), a multilayer substrate (40) characteristic of the present invention, etc. are shown. Note that a conductive path (14) is also formed on the insulated metal substrate (12) below the multilayer substrate (40).

The insulated metal substrate (12) is made of aluminum, the surface of which is alumite-treated by anodizing, and its main surface is coated with an adhesive insulating resin such as epoxy resin or polyimide resin.

The conductive path (14) and the external lead pad l' (18) are formed into a predetermined pattern by photo-etching a copper foil that has been previously attached to the insulated metal substrate (12), and is particularly suitable for the bus (18).
A portion of the conductive path (I4) separated by the conductive path (14) shown as 16) is connected by dipping with an aluminum wire (22). Further, a conductive path (14) at ground potential is connected to the substrate metal (20).

Chip elements are used for the first and second gate arrays (24030), microcomputer (26), memory (28), and other peripheral integrated circuits (32), and they are arranged on predetermined conductive paths (14). It is fixed with Ag paste. Further, the chip resistor (34) and the chip capacitor are soldered and fixed to a predetermined conductive path (14).

Note that the functions of the integrated circuit elements have been explained in the conventional example section, so a description thereof will be omitted.

Next, referring to FIG. 2, a multilayer substrate (4
0) will be explained.

The multilayer substrate (40) is made of resin such as glass epoxy, paper epoxy, paper phenol, polyimide, etc. with a thickness of 0.6 mm to 1.0 mm, and as shown in the figure, the first and second gate arrays (24) ( 30), a hole (42) and a notch (42) are formed to expose the microcomputer (26) and memory (28) chips. As will become clear from the following explanation, this hole (4
2) is formed to arrange bonding pads 7F in multiple layers around an integrated circuit element such as a microcomputer (26), and is limited to holes as long as the shape substantially achieves the purpose. It is not something that will be done.

In addition, conductive paths (44) such as address buses and data buses are formed on both sides of the multilayer substrate (40) by a well-known method, as shown in part, and through holes (46) are formed at appropriate positions. ) are connected by.

A portion of the predetermined conductive path (44) is formed to extend to the peripheral edge of the multilayer substrate (40), forming a pad (48) that is bonded to a pad formed on the insulated metal substrate (12). A part of the other predetermined conductive path (44) is formed by a hole (42).
), the first and second gate arrays <24) (30), a microcomputer (26);
A pad (50) is formed to be connected by bonding to the electrode of the memory (28). Said pad (48)
And its wire bonding process is a multilayer board (40
) can be omitted by forming a solder bump at a predetermined position on the back surface of the insulating metal substrate (12) and connecting the bump to a corresponding pad formed on the insulated metal substrate (12).

The present invention will be explained in more detail with reference to FIG.

This figure is a cross-sectional view taken along the line I-I of FIG. 1 partially shown as a side view for ease of understanding, and the hybrid integrated circuit device of the present invention includes a metal substrate (10), an insulating resin layer (12), A conductive path (14) and an external lead pad (18) formed on this insulating resin layer (12), and first and second gates fixed on the conductive path (14) via an Ag paste layer (15). Array (24) (30), microcomputer (26)
, a main board consisting of a memory (28), a multilayer board (40) formed with a hole (42) (shown in side view) for the integrated circuit chip, and this multilayer board (40) as a main board. It is shown with an insulating adhesive resin layer (60) that is insulatingly bonded to.

The insulating adhesive resin layer (60) is formed by coating an epoxy resin, by coating a solder resist, or by coating the layer with a thickness of 0.
It is formed by an adhesive resin-impregnated sheet that is made by impregnating Japanese paper of about 5 mm with an adhesive resin, such as epoxy resin, and cutting it into approximately the same shape as the multilayer substrate (40). In particular, the adhesive resin-impregnated sheet has no adhesive properties at room temperature, so it is easy to handle, and when heated to about 125°C, the impregnated resin melts and is further thermoset to bond the multilayer board (40) and the main board. Compared to the case of applying resin or resist, not only can better insulation be obtained, but also the adjustment and application processes can be omitted, which simplifies the process of adhering the multilayer substrate (40). has.

After forming the insulating adhesive resin layer (60), the multilayer substrate (40) is disposed on the main substrate by engaging guide posts (not shown) formed on the main substrate and bonded under predetermined temperature conditions. Then, an Ag paste layer (15) is formed by a stamping method in a predetermined area exposed by the hole (42) of the multilayer substrate (40), and the first and second gate arrays are formed on the Ag paste layer (15). Integrated circuit elements such as (24) (30), a microcomputer (26), and a memory (28) are arranged.

Then, when the main substrate is heated to melt the Ag paste layer (15) and fix the integrated circuit element on the conductive path (14), the first and second Gate array (24030), microcomputer (26
), around the memory (28) are arranged in two layers (to be connected to the electrodes of these integrated circuit elements), and the conductive path (14) on the insulated metal substrate (12) or the multilayer substrate ( 40) It becomes possible to wire bond to any of the conductive paths (44) on the top.

The bonding wire connecting the electrode of the integrated circuit element and the conductive path (14) is reference number (36), and the bonding wire connecting the electrode of the integrated circuit element and the rose l' (50) of the multilayer substrate (40) is reference number (52), and a bonding wire connecting the band (48) of the multilayer substrate (40) and the conductive path (14) is indicated by the reference number (54).

As described above, in the present invention, where address buses, data buses, etc. are connected via conductive paths formed on a multilayer substrate, the conductive paths (14) on the main substrate can be connected at a maximum of two locations. This can be done by wire bonding.

Further, the conductive path (44) of the multilayer board (40) is connected to any conductive path (44) on the main board by wire bonding at one location.
), and the number of relay pads can be significantly reduced. Furthermore, this allows the layout of the microcomputer and its peripheral circuit elements to be standardized and simplified as shown in the figure.

Here, an example of the process for realizing the hybrid integrated circuit device of the present invention will be briefly described below.

Solder printing Medium chip resistor) 2) Solder melting (210'C) => Cleaning Adhesive resin impregnated sheet and multilayer board arrangement 2) Multilayer board adhesion (125
°C) → Ag paste application to) Die bonding (integrated circuit chip) <Ag cure (155°C)
) During wire bonding Resin coat (125°
C) ==> with external leads) Casing The present invention has been described based on one embodiment, but the present invention is applicable to a microcomputer and its peripheral circuits in which, for example, the material and layout of the insulating adhesive resin layer should be standardized. It is clear to those skilled in the art that the scope, type, etc. of the elements can be variously modified and the present invention is not limited to the embodiments.

()) Effects of the Invention As described above, according to the present invention, (1) The number of wire bonding is reduced, so the process is simplified. This also improves the reliability of the hybrid integrated circuit device.

(2) Long span connections are possible, and the number of relay pads is reduced, which improves packaging density.

(3) Since the predetermined electrodes of the microcomputer and its peripheral circuit elements are connected by the shortest distance, there is no problem caused by wiring capacitance.

(4) Since the layout of the microcomputer and its peripheral circuit elements can be made smaller and standardized, pattern design of the hybrid integrated circuit device becomes easier.

(5) Since the pads are arranged in multiple layers around the multi-bin integrated circuit element, the electrodes of the integrated circuit element and the corresponding bus can be connected over the shortest distance.

[Brief explanation of the drawing]

Fig. 1 is a plan view of an embodiment of the present invention, Fig. 2 is a plan view of a multilayer board characteristic of the present invention, Fig. 3 is a sectional view taken along line I-1 in Fig. 1, and Fig. 4 is a conventional Example top view. (12)...Insulated metal substrate, (18)...Nobed for external leads...bonding wire, element, (34)...chip resistor, (42)...hole. (14) (44) --- Conductive path 1, (22) (36) (52) (54) (24) ~
(32)...Integrated circuit (40)...Multilayer board,

Claims (5)

[Claims] (1) A conductive path is formed in a predetermined shape, and an insulated metal substrate is provided with at least a memory and a microcomputer fixedly mounted on a predetermined position of the conductive path, and a region corresponding to the fixed region of the memory, microcomputer, etc. is cut out. A multilayer substrate with bonding pads formed on the peripheral edge of the wiring pattern including the cutout, common address line, data line, etc., and an insulating adhesive for fixing this multilayer substrate onto an insulated metal substrate. 1. A hybrid integrated circuit device comprising at least a resin layer, wherein electrodes of elements such as the memory and microcomputer are wire-bonded to bonding pads of a multilayer substrate formed adjacent to these elements. (2) The multilayer substrate is glass epoxy, paper epoxy, P
2. The hybrid integrated circuit device according to claim 1, wherein the hybrid integrated circuit device is formed of resin such as CB or polyimide. (3) The hybrid integrated circuit device according to claim 1, wherein an epoxy resin or a solder resist is used for the insulating adhesive resin layer. (4) The hybrid integrated circuit device according to claim 1, wherein chip elements are used for the memory and the microcomputer. (5) The hybrid integrated circuit device according to claim 4, wherein the thickness of the multilayer substrate is substantially equal to the mounting height of the elements such as the memory and the microcomputer.