JPH0487430A - Frame synchronization detecting circuit - Google Patents

Abstract

PURPOSE:To prevent the counter station alarm from being generated erroneously even when there are many transmission line errors, and a synchronized state and a step-out state are repeated by setting the number of protective stages for detecting a counter station alarm signal to a larger value, when a frame pattern detecting circuit does not detect a frame pattern. CONSTITUTION:A decoder 9 decodes a signal from a transmission line 1 and outputs it. A frame pattern detecting circuit 2 detects a prescribed frame pattern and takes frame synchronization, outputs a logical signal of a high level, does not detect a frame pattern, and outputs a logical signal of a low level at the time of a step-out state. When a code error is detected an error detecting circuit 3 outputs a logical signal of a high level as a transmission line error alarm. When a value of a counter station alarm signal is '1' continuously five times, a counter station alarm detecting circuit 4 outputs a logical signal of a high level as a counter station alarm, and when said value is '0' continuously three times, said circuit outputs a logical signal of a low level as a counter station alarm release. Also, when the frame pattern detecting circuit 2 is outputting the logical signal of a low level, the number of protective stages is set to the number being larger than 5.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a frame synchronization detection circuit, and more particularly to a frame synchronization detection circuit that is improved in terms of issuing an alarm related to a transmission path error.

[Conventional technology]

An example of a conventional frame synchronization detection circuit is shown in FIG. The decoder 90 receives the encoded signal from the transmission line 10, decodes it, and outputs it. The frame pattern detection circuit 20 receives a signal from the decoder 90, and outputs a logic signal at a high level when a predetermined frame pattern is detected, and a logic signal at a low level when a predetermined frame pattern is not detected. The error detection circuit 30 includes a decoder 90
When the frame pattern detection circuit 20 outputs a low-level logic signal, it is reset and outputs a low-level logic signal. Output.

The match alarm detection circuit 40 receives a signal from the decoder 90, detects a match alarm signal, and outputs a high-level logic signal. Logic circuit 701 is frame pattern detection circuit 2
0 and the error detection circuit 30 output a high level logic signal, a high level logic signal is output. The logic circuit 702 outputs a high level logic signal when the logic circuit 701 and the match alarm detection circuit 40 output a high level logic signal.

Here, logic circuits 701 and 702 are for determining the priority of each alarm. That is, the logic circuit 701 is
When frame synchronization is achieved, that is, when the frame pattern detection circuit 20 outputs a high-level logic signal, and when the error detection circuit 30 detects an error in the transmission line code and outputs a high-level logic signal. , outputs a high-level logic signal as a transmission path error alarm. In addition, the logic circuit 702 outputs a high-level logic signal as a match alarm when the match alarm detection circuit 40 detects a match alarm signal in a state where a transmission path error is detected and the logic circuit 701 is outputting a high-level logic signal. Output. Therefore, the priority of each alarm is frame synchronization loss, transmission path error, and game alarm.

[Problem to be solved by the invention]

In such a conventional frame synchronization detection circuit, when there are many transmission path errors, the logic circuit 701 does not output a signal indicating a transmission path error alarm, but the logic circuit 702 outputs a signal indicating detection of a game alarm signal. There was a problem with being exposed.

The interval from a synchronized state to an unsynchronized state due to a transmission path error is expressed as an average misframe interval Tm given by the following equation.

Tm = (1 + rXPe) Total number of bits of the frame TI = clock period Here, for example, the transmission path error rate Pe is Pe = 1.0 x 104
In this case, the average misframe interval Tm is about 1 second, and a synchronized state and an unsynchronized state are alternately repeated at such short intervals. By the way, in the above-mentioned frame synchronization detection circuit, detection of a transmission path error is stopped when frame synchronization is not established, so when the frame pattern detection circuit 20 does not detect a frame pattern, the low output from the detection circuit 20 is The error detection circuit 30 is reset by the level logic signal. Therefore, when synchronization and non-synchronization are repeated at short intervals as described above, the error detection circuit 30 is reset and no transmission path error alarm is issued even when synchronization is achieved. On the other hand, since the match alarm detection circuit 40 is always in operation, even if a transmission line error alarm is not issued, when a match alarm signal is detected, it outputs a high level logic signal as a match alarm. In other words, even though no transmission line error alarm has been issued, a game alarm is erroneously issued in violation of the priority order.

Therefore, if the transmission equipment is designed to switch from the working interface to the backup interface when a match alarm is issued in a state where frame synchronization is lost, conventional frame synchronization detection circuits may accidentally switch the interface due to a false match alarm. I'll have to switch.

The purpose of the present invention is to solve these problems and to provide frame synchronization that prevents a game alarm from being erroneously issued even when there are many errors in the transmission path and synchronization is repeatedly achieved and synchronized at short intervals. The object of the present invention is to provide a detection circuit.

[Means to solve the problem]

The first invention each receives a signal from a transmission line,
A frame synchronization detection circuit that includes a frame pattern detection circuit that detects a predetermined frame pattern for frame synchronization and an error detection circuit that detects an error in a transmission line code receives a signal from the transmission line and plays a game. A game alarm detection circuit that detects an alarm signal and sets the number of protection stages for detecting the game alarm signal to a larger value when the frame pattern detection circuit does not detect the predetermined frame pattern. It is characterized by

The second invention each receives a signal from a transmission line,
In a frame synchronization detection circuit comprising a frame pattern detection circuit that detects a predetermined frame pattern for frame synchronization and an error detection circuit that detects an error in a transmission line code, the frame pattern detection circuit a timer that outputs a predetermined signal when the predetermined frame pattern is detected; a timer that receives the signal from the transmission line and detects an error in the transmission line code, and when the error rate of the transmission line code is less than or equal to a predetermined value; a transmission line code error detection circuit that outputs a predetermined signal; a logic circuit that outputs a predetermined signal when the timer outputs the predetermined signal and the transmission line code error detection circuit outputs the predetermined signal; , receives a signal from the transmission path to detect a game alarm signal, and when the frame pattern detection circuit does not detect the predetermined frame pattern, sets the number of protection stages for detecting the game warning signal to a larger value. and a match alarm detection circuit that sets the number of protection stages to the original value when the logic circuit outputs the predetermined signal.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a frame synchronization detection circuit according to the first invention. A signal in a predetermined frame format is transmitted on each transmission path, and it is assumed that, as an example, a signal in a primary group 1.544 Mbps frame format is transmitted on transmission path 1. This frame format has a multi-frame configuration of 12 frames as shown in FIG.

The decoder 9 receives the encoded signal from the transmission path l,
Decrypt and output. The frame pattern detection circuit 2 receives the signal from the decoder 9, and detects the synchronization bits "100011011" included in the 1st to 11th frames in FIG.
Frame synchronization is achieved by detecting a predetermined frame pattern of 10''.

When this pattern is detected, a high-level logic signal is output, and when the frame pattern is not detected and the synchronization is out of synchronization, a low-level logic signal is output. The error detection circuit 3 receives the signal from the decoder 9, and converts the transmission line code (-AMI in the case of 1.544 Mbps)
code or B8ZS code, etc.).
When the transmission path error rate is 10xio-3 or more, a high-level logic signal is output as a transmission path error alarm when code errors are detected in 5 or more multiframes out of 216 multiframes (324ms) three times in a row. Error detection circuit 3
also receives the output signal of the frame pattern detection circuit 2,
When it is low level, it is reset and outputs a low level logic signal. The match alarm detection circuit 4 receives the signal from the decoder 9 and checks the value of the 12th frame (SEND) of the 12 multi-frames shown in FIG. A high level logic signal is output as a match alarm when the number of times is "1pa", and a low level logic signal is output as a match alarm cancellation when the number is "0°" three times in a row. And frame pattern detection circuit 2
When outputting a low-level logic signal, the number of protection stages is set to a number greater than five.

Logic circuit 7L 72 is for determining the priority order of each alarm (frame synchronization loss, transmission path error, game alarm in order), and logic circuit 71 is for determining the priority of each alarm (in the order of frame synchronization loss, transmission line error, and game alarm), and logic circuit 71 indicates that both frame pattern detection circuit 2 and error detection circuit 3 are at high level. When a logic signal of 1 is being output, a high level logic signal is output as a transmission path error alarm. On the other hand, the logic circuit 72 outputs a high-level logic signal as a match alarm when the logic circuit 71 outputs a high-level logic signal and the match alarm detection circuit 4 also outputs a high-level logic signal.

Next, the operation will be explained. If the transmission path error rate increases and the frame pattern detection circuit 2 is unable to detect the predetermined frame pattern, and the frame synchronization is lost, the frame pattern detection circuit 2 outputs a low level logic signal. As a result, the error detection circuit 3 is reset by this signal and outputs a low level logic signal, while the game alarm detection circuit 4 sets the number of protection stages to a value greater than five.

In other words, when the frame synchronization is lost, the number of protection stages of the game alarm detection circuit 4 is set to a large value, so even when there are many transmission path errors and the synchronized state and the lost state are repeated, the game alarm can be detected. This prevents the circuit 4 from erroneously issuing a game alarm.

FIG. 2 is a block diagram showing an embodiment of a frame synchronization detection circuit according to the second invention. This frame synchronization detection circuit includes a timer 5 in addition to the frame synchronization detection circuit shown in FIG.
, a transmission path code error detection circuit 6, and a logic circuit 8, and further provides a new function to the game alarm detection circuit 400.

The timer 5 outputs a high-level logic signal when the frame synchronization state continues for a certain period of time and the frame pattern detection circuit 2 continues to output a high-level logic signal for a certain period of time. The transmission line code error detection circuit 6 detects errors in the transmission line code, and outputs a high-level logic signal if the error rate is below a predetermined error rate guaranteed on the transmission line 1.

The logic circuit 8 outputs a high-level logic signal when both the detection circuit 6 and the timer 5 output high-level logic signals. In addition to the function of the game alarm detection circuit 4 described above, the game alarm detection circuit 400 also performs a function based on the value of the protection stage number set to a large value when the logic circuit 8 outputs a high level logic signal. Return to 5.

In the frame synchronization detection circuit according to the second invention configured as described above, the error rate of the transmission path decreases after the out-of-synchronization state occurs and the number of protection stages in the game alarm detection circuit 400 is set to a value larger than 5. However, when synchronization is achieved and this state continues for a certain period of time, the timer 5 outputs a high-level logic signal. - On the other hand, the transmission line code error detection circuit 6 detects errors in the transmission line code regardless of the state of frame synchronization, and if the error rate is less than the predetermined error rate guaranteed on the transmission line 1, the high level is detected. Outputs a logic signal. In other words, when the error rate of the transmission path decreases and the frame synchronization state continues for a certain period of time, the logic circuit 8 outputs a high-level logic signal to the game alarm detection circuit 400, and the detection circuit 400 When the value of the protection stage is changed to the original 5
Return to In this way, in the frame synchronization detection circuit according to the second invention, when the frame synchronization is lost, the number of protection stages of the game alarm detection circuit is set to a large value, which not only prevents the issuance of a false game alarm, but also protects the transmission path. The error rate of
When frame synchronization becomes stable, the number of protection stages is returned to its original value, making it possible to issue an appropriate game warning.

〔Effect of the invention〕

As explained above, the first invention includes a frame pattern detection circuit that receives signals from a transmission line and detects a predetermined frame pattern for frame synchronization, and an error detection circuit that detects errors in transmission line codes. In a frame synchronization detection circuit having
It is equipped with a match alarm detection circuit that sets the number of protection stages for detecting a match alarm signal to a larger value.

Therefore, according to the frame synchronization detection circuit based on the first invention, when the frame synchronization is lost, the number of protection stages of the game alarm detection circuit is set to a large value, so that there are many transmission path errors and the synchronization is established. Even when a situation in which the error occurs repeatedly, the game game alarm detection circuit is prevented from erroneously issuing a game game alarm.

The second invention each receives a signal from a transmission line,
In a frame synchronization detection circuit that includes a frame pattern detection circuit that detects a predetermined frame pattern for frame synchronization and an error detection circuit that detects errors in transmission line codes, the frame pattern detection circuit detects a predetermined frame pattern for a certain period of time.
There is a timer that outputs a predetermined signal when a predetermined frame pattern is detected, and a timer that receives a signal from the transmission line and detects an error in the transmission line code, and when the error rate of the transmission line code is less than a predetermined value, a timer that outputs a predetermined signal. a transmission line code error detection circuit that outputs a signal; a logic circuit that outputs a predetermined signal when the timer outputs the predetermined signal and the transmission line code error detection circuit outputs the predetermined signal; When the signal is received and the game alarm signal is detected, and the frame pattern detection circuit does not detect a predetermined frame pattern, the number of protection stages for detecting the game alarm signal is set to a larger value;
The apparatus includes a match alarm detection circuit that sets the number of protection stages to the original value when the logic circuit outputs a predetermined signal.

Therefore, according to the frame synchronization detection circuit based on the second invention, when the frame synchronization is lost, the number of protection stages of the game alarm detection circuit is set to a large value, not only preventing the issuance of a false game alarm, but also preventing transmission. The error rate of the path is reduced,
When frame synchronization becomes stable, the number of protection stages is returned to its original value, making it possible to issue an appropriate game warning.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the frame synchronization detection circuit according to the first invention, FIG. 2 is a block diagram showing an embodiment of the frame synchronization detection circuit according to the second invention, and FIG. 4 is a block diagram showing an example of a conventional frame synchronization detection circuit. FIG. 4 is a block diagram showing an example of a conventional frame synchronization detection circuit. 1...Transmission path 2...Frame pattern detection circuit 3...Error detection circuit 4.400...Game alarm detection circuit 5...Timer 6... Transmission line code error detection circuit 8, 71, 72, logic circuit 9...decoder

Claims (2)

[Claims] (1) A frame synchronization detection circuit that includes a frame pattern detection circuit that receives signals from a transmission path and detects a predetermined frame pattern for frame synchronization, and an error detection circuit that detects errors in transmission path codes. When the signal from the transmission path is received and the game alarm signal is detected, and the frame pattern detection circuit does not detect the predetermined frame pattern, the number of protection stages for detecting the game alarm signal is increased. A frame synchronization detection circuit characterized by comprising a game alarm detection circuit that sets a value to a value. (2) A frame synchronization detection circuit that includes a frame pattern detection circuit that receives signals from a transmission path and detects a predetermined frame pattern for frame synchronization, and an error detection circuit that detects errors in transmission path codes. a timer that outputs a predetermined signal when the frame pattern detection circuit detects the predetermined frame pattern for a certain period; and a timer that receives the signal from the transmission line to detect an error in the transmission line code, and a transmission line code error detection circuit that outputs a predetermined signal when the code error rate is below a predetermined value; the timer outputs the predetermined signal; and the transmission line code error detection circuit outputs the predetermined signal. a logic circuit that outputs a predetermined signal when the signal is output; and a logic circuit that receives the signal from the transmission line to detect a game alarm signal, and when the frame pattern detection circuit does not detect the predetermined frame pattern, generates the game alarm signal. A game alarm detection circuit that sets the number of protection stages for signal detection to a larger value and sets the number of protection stages to the original value when the logic circuit outputs the predetermined signal. Frame synchronization detection circuit.