JPH0488435A - Measurement system for total execution clock quantity by instruction - Google Patents

Measurement system for total execution clock quantity by instruction

Info

Publication number
JPH0488435A
JPH0488435A JP2197107A JP19710790A JPH0488435A JP H0488435 A JPH0488435 A JP H0488435A JP 2197107 A JP2197107 A JP 2197107A JP 19710790 A JP19710790 A JP 19710790A JP H0488435 A JPH0488435 A JP H0488435A
Authority
JP
Japan
Prior art keywords
instruction
clock
storage area
measurement
clock quantity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2197107A
Other languages
Japanese (ja)
Inventor
Mamoru Hirono
守 廣野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2197107A priority Critical patent/JPH0488435A/en
Publication of JPH0488435A publication Critical patent/JPH0488435A/en
Pending legal-status Critical Current

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  • Executing Machine-Instructions (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE:To measure the total clock quantity from the execution start to the end of a couple of instructions and the clock quantities by the instructions by adding the output of a clock measuring means to an integral value storage area only when an instruction decision means decides a coincidence. CONSTITUTION:The instruction decision means 13 decides whether an instruction being executed currently is the same as an instruction in a measurement instruction storage area 13 in an instruction emulation figure 17. A clock quantity measuring means 14 measures the clock quantity from the execution start of an instruction in an instruction emulation part 11 to the execution start of a next instruction at all times. Then a clock quantity integrating means 15 adds the output value of the clock quantity measuring means 14 to an integral value storage area 16 only when the instruction decision means 13 decides that the instruction being executed currently is an instruction to be measured. Consequently, the load rate of a CPU, i.e. the time of effective processing by the CPU and the execution time of stand-by instructions in each unit time are found by the measurement.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は命令別実行クロック総数計量方式、特に、マイ
クロプロセッサシステム開発用のインサーキットエミニ
レータの命令別実行クロック総数計量方式に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for measuring the total number of execution clocks per instruction, and particularly to a method for measuring the total number of execution clocks per instruction in an in-circuit emulator for microprocessor system development.

〔従来の技術〕[Conventional technology]

従来の技術では、−群の命令の実行開始から実効終了ま
での全クロック数を計量する手段はあったが、命令側に
クロック数を計量することは不可能であった。
In the prior art, there was a means to measure the total number of clocks from the start of execution to the end of effective execution of instructions in the - group, but it was impossible to measure the number of clocks on the instruction side.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

マイクロプロセッサシステムの開発では、システムの性
能、特に処理速度が非常に重要な評価要素となる。−成
約にいって、性能はただ速ければよいというものではな
く、コストとのトレードオフからそのシステムにとって
の最適速度が決まる。処理速度を最適化させる方法とし
て、現行のシステムの各種負荷分布を測定して悪い点を
改良していくという方法が多くとられる。この際、以下
の様な値の測定は非常に重要となる。
In the development of microprocessor systems, system performance, especially processing speed, is a very important evaluation factor. - When it comes to making a deal, it is not just about performance that is fast; the optimum speed for the system is determined by the trade-off with cost. A commonly used method for optimizing processing speed is to measure the various load distributions of the current system and improve the weak points. At this time, measurement of the following values is very important.

(1)CPUの負荷率、つまり、単位時間内にCPUが
実効的な処理をしている時間。
(1) CPU load factor, that is, the time during which the CPU performs effective processing within a unit time.

(2)一つ以上のコプロセッサを使用しているシステム
において、コプロセッサ間の負荷分布。
(2) Load distribution among coprocessors in a system using one or more coprocessors.

つまり、単位時間内の各コプロセッサの処理時間。That is, the processing time of each coprocessor within a unit of time.

上記(1)は通常、待機命令(ホールド命令等)の実行
時間を測定することにより、また上記(2)は、各コプ
ロセッサ用の命令の処理時間を測定することにより求め
ることができる。ところが、マイクロプロセッサシステ
ムの開発に使用されるインサーキットエミュレータには
従来このような命令側の総処理時間を測定する機能がな
く、この様な測定を簡単にはおこなうことができないと
いう欠点があった。
The above (1) can usually be obtained by measuring the execution time of a standby instruction (hold instruction, etc.), and the above (2) can be obtained by measuring the processing time of an instruction for each coprocessor. However, in-circuit emulators used in the development of microprocessor systems have traditionally lacked the ability to measure the total processing time on the instruction side, and have had the disadvantage that such measurements cannot be easily performed. .

〔課題を解決するための手段〕[Means to solve the problem]

本発明の命令側実行クロック総数計量方式は、測定対象
命令を測定命令格納領域へ登録する測定命令登録手段と
、現在実行中の命令が前記測定対象命令かを判定する命
令判定手段と、各命令の実行に何クロック要したかを計
量するクロック数計量手段と、前記命令判定手段が一致
と判定したときのみ前記クロック計量手段の出力を積算
値格納領域へ加算してゆくクロック数積算手段とを含ん
で構成される。
The method for measuring the total number of execution clocks on the instruction side of the present invention includes: measurement instruction registration means for registering measurement target instructions in a measurement instruction storage area; instruction determination means for determining whether the currently executed instruction is the measurement target instruction; a clock number measuring means for measuring how many clocks are required for execution of the instruction; and a clock number integrating means for adding the output of the clock measuring means to an integrated value storage area only when the instruction determining means determines that there is a match. It consists of:

〔実施例〕 第1図は本発明の一実施例を示すブロック図である。〔Example〕 FIG. 1 is a block diagram showing one embodiment of the present invention.

測定命令登録手段11は、インサーキットエミュレータ
のコンソール等から測定対象となる命令の指定をうける
と、それを対象CPUの機械語命令のビット列に変換し
て、測定命令格納領域12に格納する。この変換は、い
わゆる「アセンブル」と呼ばれる変換であって公知のも
のである。
When the measurement instruction registration means 11 receives an instruction to be measured from the console of an in-circuit emulator, it converts it into a bit string of a machine language instruction of the target CPU and stores it in the measurement instruction storage area 12. This conversion is a well-known conversion called "assembly."

変換されたビット列の各ビットの値は、「1」か「0」
か「1,0どちらでもよい」のいづれかである。「1,
0どちらでもよい」は、命令のアドレス部の値は任意で
よい時等に用いる。
The value of each bit of the converted bit string is "1" or "0"
or "1 or 0 is fine." ``1,
0 or 0 is used when the value of the address part of the instruction can be arbitrary.

測定命令格納領域12は、メモリ上の1の領域であって
測定対象命令の機械語のビットパターンが格納される。
The measurement instruction storage area 12 is one area on the memory, and stores the bit pattern of the machine language of the instruction to be measured.

命令判定手段13は、命令エミュレーション図17で現
在実行中の命令と測定命令格納領域13の命令が同一が
どうかを判定する。判定は、2つのビット列の比較であ
ってその方法は公知のものである。
The instruction determining means 13 determines whether the instruction currently being executed in the instruction emulation diagram 17 and the instruction in the measurement instruction storage area 13 are the same. The determination is a comparison of two bit strings, and the method is known.

クロック数計量手段14は、命令エミュレーション部で
の命令の実行開始から次の命令の実行開始までのクロッ
ク数を常に測定している。
The clock count measuring means 14 constantly measures the number of clocks from the start of execution of an instruction in the instruction emulation unit to the start of execution of the next instruction.

クロック数積算手段15は、命令判定手段13が現在実
行中の命令が測定対象命令であると判定したときのみ、
クロック数計量手段14の出力値を積算値格納領域16
へ加算していく。
The clock number accumulating means 15 only when the instruction determining means 13 determines that the currently executed instruction is the measurement target instruction.
The output value of the clock number measuring means 14 is stored in the integrated value storage area 16.
Add to.

積算値格納領域16は、メモリ上にとられた1領域であ
って、その中のデータは、現時点での測定対象命令の総
クロック数を表している。
The integrated value storage area 16 is an area reserved on the memory, and the data therein represents the total number of clocks of the instruction to be measured at the present time.

〔発明の効果〕〔Effect of the invention〕

本発明は、マイクロプロセッサシステムに関する以下の
様な性能評価を簡単に行なうことが出来るという効果が
ある。
The present invention has the advantage that the following performance evaluation regarding a microprocessor system can be easily performed.

(1)CPUの負荷率。つまり、単位時間内に、CPU
が実効的な処理をしている時間。待機命令(ホールド命
令等)の実行時間を測定することにより求める。
(1) CPU load factor. In other words, within a unit time, the CPU
is the time during which it is performing effective processing. It is obtained by measuring the execution time of a standby instruction (hold instruction, etc.).

(2)一つ以上のコプロセッサを使用しているシステム
において、コプロセッサ間の負荷分布。
(2) Load distribution among coprocessors in a system using one or more coprocessors.

つまり、単位時間内の、各コプロセッサの処理時間。各
コプロセッサ用の命令の処理時間を測定することにより
もとめる。
In other words, the processing time of each coprocessor within a unit time. This is determined by measuring the processing time of instructions for each coprocessor.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を示すブロック図である。 11・・・測定命令登録手段、12・・・測定命令格納
領域、13・・・命令判定手段、14・・・クロック数
計量手段、15・・・クロック数積算手段、16・・・
積算値格納領域、17・・・命令エミュレーシeン部、
18・・・クロック。
FIG. 1 is a block diagram showing one embodiment of the present invention. DESCRIPTION OF SYMBOLS 11... Measurement instruction registration means, 12... Measurement instruction storage area, 13... Instruction determination means, 14... Clock number measuring means, 15... Clock number accumulating means, 16...
integrated value storage area, 17...instruction emulation section;
18...Clock.

Claims (1)

【特許請求の範囲】[Claims]  測定対象命令を測定命令格納領域へ登録する測定命令
登録手段と、現在実行中の命令が前記測定対象命令かを
判定する命令判定手段と、各命令の実行に何クロック要
したかを計量するクロック数計量手段と、前記命令判定
手段が一致と判定したときのみ前記クロック計量手段の
出力を積算値格納領域へ加算してゆくクロック数積算手
段とを含むことを特徴とする命令別実行クロック総数計
量方式。
Measurement instruction registration means for registering the instruction to be measured in a measurement instruction storage area, instruction determination means for determining whether the instruction currently being executed is the instruction to be measured, and a clock for measuring the number of clocks required to execute each instruction. and a clock number accumulating means that adds the output of the clock measuring means to an integrated value storage area only when the instruction determining means determines that there is a match. method.
JP2197107A 1990-07-25 1990-07-25 Measurement system for total execution clock quantity by instruction Pending JPH0488435A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2197107A JPH0488435A (en) 1990-07-25 1990-07-25 Measurement system for total execution clock quantity by instruction

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2197107A JPH0488435A (en) 1990-07-25 1990-07-25 Measurement system for total execution clock quantity by instruction

Publications (1)

Publication Number Publication Date
JPH0488435A true JPH0488435A (en) 1992-03-23

Family

ID=16368850

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2197107A Pending JPH0488435A (en) 1990-07-25 1990-07-25 Measurement system for total execution clock quantity by instruction

Country Status (1)

Country Link
JP (1) JPH0488435A (en)

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