JPH0488450A - Memory access controller - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a memory access control device inserted between an external control unit such as a CPU and an external memory such as a RAM.

(Prior Art) In an information processing system such as a microcomputer, a CPU (central processing unit) directly accesses data to an external memory such as a RAM when a contract is concluded. However, when reading a large number of data stored in consecutive addresses of external memory, or when repeatedly reading data from a pre-specified address, there is a memory between the CPU and external memory. An access control device is inserted to cause this memory access control device to execute actual data access processing to the external memory.

FIG. 3 is a block diagram showing the main parts of an information processing system incorporating such a memory access control device. The CPU 2 is connected to the data bus 3a.

It is connected to a memory access control device 6 via an address bus 4a and various control lines 5a. The memory access control device 6 includes a data bus 3b, an address bus 4b,
It is connected to an external memory 7 composed of a RAM or the like via various control lines 5b.

Note that in this information processing system, the external memory 7
is configured with dual-port RAM, allowing data access from another CPU or control device.

The memory access control bag W6 is formed of a semi-custom LIS called a gate array, and a memory access circuit 8 and an internal memory 9 are housed inside. The internal memory 9 has a function of temporarily storing control data such as addresses necessary for data accessing the external memory 7 input from the CPU 2 and access data read from the external memory 7. Furthermore, the memory access circuit 8 has a function of data accessing the actual external memory 7 based on control data set in the internal memory 9 and storing the obtained access data in the internal memory 9.

In such an information processing system, the CPU 2 sets various control data in the internal memory 9 of the memory access control device 6 in advance, and then sends an access command to the memory access circuit 8 or the internal memory 9. Accessing the external memory 7 based on the control data,
The resulting access data is written into the internal memory 9. Thereafter, the CPU 2 performs data access to the internal memory 9 and fetches necessary data.

In this way, since the actual access processing to the external memory 7 is performed using the memory access control device 6 formed of, for example, a gate array, the processing load on the CPU 2 can be significantly reduced.

However, the memory access control device 6 configured as shown in FIG. 3 still has the following problems.

That is, if some abnormality occurs and the CPU 2 is unable to obtain correct data, the data bus 3a, address bus 4a, various control lines 5a, or memory access control device connecting the CPU 2 and the memory access control device 6 6 itself, or a data bus 3b connecting this memory access control device 6 and an external memory 7, and an address bus 4.
b. Failure or poor connection of various control lines 5b or the external memory 7 itself is considered.

Generally, when an error occurs in the process of accessing an external memory from the CPU, a diagnostic program stored in a ROM or the like is activated in advance to determine the cause of the failure. In this diagnostic program,
Known data is written into a pre-designated address of an external memory via an IF, and later the data stored at the corresponding address is read to check whether the read data matches the written known data. By running this kind of diagnosis, you can determine whether the external memory itself is abnormal or whether the CPU
It can be determined whether there is an abnormality in each bus or control line connecting the computer and external memory.

However, as shown in FIG. 3, the CPU 2 and external memory 7
If the memory access control device 6 is interposed between the external memory 7 and the memory access control device 6, it is not possible to determine whether it is the memory access control device 6 that is abnormal in the external memory 7 by simply running the above-mentioned general diagnostic program. or CPU2. Each bus 3a connects the memory access control device 6 and the external memory 7.

It is difficult to distinguish whether 3b, 4a, 4b and each control line 5a, 5b are abnormal.

In order to accurately investigate the cause of the abnormality, the procedure for the memory access circuit 8 in the memory access control device 6 to access the external memory 7 and the input/output to and from the memory access control device 66 and the external memory 7 are necessary. We need to understand the actual data. Therefore, elucidating the cause of this abnormality required specialized knowledge, advanced technology, and a great deal of time and effort.

Furthermore, as mentioned above, the memory access control device 6 itself has been made into a gate array, and other electronic components have been mounted in a high-density manner, resulting in subdivision of the board pattern and reduction in pad spacing. It has become difficult to detect abnormalities, and there is an increasing need to identify abnormalities using methods other than visual inspection.

(Problems to be Solved by the Invention) As described above, according to the conventional memory access control device,
- If an abnormality occurs during indirect access processing from the CPU to the external memory via the memory access control device, it is difficult to identify the location where the abnormality has occurred even if a diagnostic program is used.

The present invention was made in view of these circumstances, and
By providing a bypass circuit that bypasses the internal memory and memory access circuit, J
The purpose of the present invention is to provide a memory access control device that allows an external control unit such as a CPIJ to directly access an external memory using this bypass circuit, and allows the location of an abnormality to be easily identified, thereby eliminating the abnormal state in a short time. do.

[Structure of the Invention] (Means for Solving the Problems) In order to solve the above problems, the present invention includes an internal memory and a memory access circuit, and the memory access circuit is set to the internal memory by an external control section. Based on the control data, the external memory connected to the outside is accessed, the obtained access data is stored in the internal memory, and after the access data is stored in the internal memory, the external control unit accesses the internal memory. A memory access control device that performs data access to the external memory includes a bypass circuit for allowing the external control unit to access data directly from the external memory without going through the external memory and the memory access circuit, and a bypass circuit for directly accessing the external memory without going through the external memory and the memory access circuit, and It is provided with a selection circuit that switches and connects an input terminal for an external memory from the memory access circuit side to the bypass circuit side.

(Function) With the memory access control device configured as described above, the external control unit can perform internal access within the memory access control device in addition to the conventional access method of indirectly accessing the external memory via the memory access control device. It becomes possible to directly access the external memory via the bypass circuit formed in the .

Therefore, in an information processing system in which this memory access control device is installed, if an abnormality occurs during data access processing in the external control unit, the diagnostic program should be started while the functions of the memory access control device are operating. After transmitting a selection signal and selecting and setting a bypass circuit using the selection circuit, the above-mentioned diagnostic program is activated to perform an abnormality analysis. In this way, the abnormal position can be more easily identified by comparing and referring to the diagnostic results of the diagnostic program executed while changing the connection conditions to the external memory.

(Example) An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the main parts of an information processing system incorporating a memory access control device according to an embodiment.

A CPU 12 serving as an external control unit is connected to a memory access control device 15 via a data bus 13a and an address bus 14a. Furthermore, this memory access control device 1
5 is a data bus 13b.

It is connected to external memory 16 via address bus 14b. In addition. In the information processing system of this embodiment, the external memory 16 is configured with a dual-baud RAM,
Allows data access from another CPU or controller.

The memory access control device 15 is formed as a semi-custom LIS called a gate array, and includes a memory access circuit 17, an internal memory 18, and a pair of data selectors 19a.

19b1 address selector 20, pair of signal selectors 2
1a, 21b, and five gates 22a.

22b, 22C, 22d, and 22e are stored.

That is, the data bus 13a connected to the data terminal of the CPU 12 is connected to the internal memory 18 and the data selector 19.
a and is connected to the common terminal of data selector 1.
9b. Further, the data bus 13b connected to the data terminal of the external memory 16 is connected to a common terminal of the data selector 19b and to a second terminal of the data selector 19a. Further, a data bus from the internal memory 18 is connected to the first terminal of the data selector 19a.
A data bus from the memory access circuit 17 is connected to the first terminal of the memory access circuit 17.

Address bus 1 connected to the address terminal of CPU 12
4 a is connected to the internal memory 18 and to the second terminal of the address selector 20 . The first terminal of this address selector 20 has a memory access circuit 1.
The address bus from 7 is connected. Also, an address bus 14 connected to an address terminal of the external memory 16
a is connected to a common terminal of the address selector 20.

Each data selector 19a, 19b and address selector 20 receive a selection signal a output from the internal memory 18.
1st. Either one of the buses connected to the second terminal is switched and connected to the bus connected to the common terminal.

Furthermore, the data selectors 19a to 19b and the address selector 20 have a bus switching function and a function of latching data and addresses. Then, each data selector 19a, 19b and address selector 2
0 normally selects the data bus and address bus from the internal memory 18g and memory access circuit 17 connected to the first terminal and connects them to the data bus and address bus on the common terminal side. When the internal memory 18 outputs, for example, the L level selection signal a, the CPU 12 side and the external memory 1 connected to the second terminal
6 side data buses 13a, 13b and address bus 1
4a, , 14b are switched and connected to each bus on the common side.

Specifically, 1. The buses are switched and connected by controlling unselected terminals among the second terminals to a high impedance state.

Further, for example, the most significant digit A15 of the address bus 14a connected to the CPU 12 is input to the decoder 23. This decoder 23 outputs a selection signal (chip select) C5 which is at L level when the most significant digit A15 is at L (0) level.
I, and when the most significant digit A15 is, for example, H (1) level, a selection signal (chip select) C32 of L level is output. The selection signal C5I output from the decoder 23 is applied to the internal memory 18 and also applied to one input terminal of the gate 22C. Further, the selection signal CS2 outputted from the decoder 23 is applied to each gate 22a, 22b, 2
It is input to one input terminal of 2d.

Further, the L level write signal WR output from the CPU 12 is input to the internal memory 18 and is also input to the gate 22.
the second input terminal of the signal selector 21a via the other input terminal of
input to the terminal. A write signal WR from the memory access circuit 17 is input to a first terminal of the signal selector 21a. The write signal WR output from the common terminal of the signal selector 21a is applied to the write terminal of the external memory 16.

Furthermore, the L level read signal RD output from the CPU 12 is input to the internal memory 18 and is also input to the gate 22.
the second input terminal of the signal selector 21b via the other input terminal of the signal selector 21b.
input to the terminal. A read signal RD from the memory access circuit 17 is input to a first terminal of the signal selector 21b.

The read signal RD output from the common terminal of the signal selector 21b is applied to the read terminal of the external memory 16.

Each signal selector 21a, 21b is connected to the internal memory 1.
Switching is controlled by the selection signal a output from 8.

That is, normally, each signal selector 21a, 21b selects the write signal WR and read signal RD output from the memory access circuit 17 and sends it to the external memory 16.

Then, when the selection signal a changes to L level, the write signal WR and read signal RD output from each gate 22a, 22b are selected and sent to the external memory 16.

Further, the ready signal READY output from the ready terminal of the external memory 16 is input to the memory access circuit 17 and is applied to the other input terminal of the gate 22d. Ready signal READY output from internal memory 18
is applied to the other input terminal of gate 22C. The ready signal READY output from either one of the gates 22c and 22d is sent to the CPU 1 via the gate 22e.
It is input to the ready terminal of No.2.

The internal memory 18 has a function of temporarily storing control data such as addresses necessary for data accessing the external memory 16 input from the CPU 12 and access data read from the external memory 16. Further, the internal memory 18 sends a selection signal a to each selector 19a to 21b based on control data set by the CPU 12. Normally, the selection signal a at H level is output. Therefore, the first terminals of each of the selectors 19a to 21b are connected to the common terminal.

The memory access circuit 17 also has a function of accessing the actual external memory 16 based on control data set in the internal memory 18 and storing the obtained access data in the internal memory 18.

In the memory access control device 15 having such a configuration, since the internal memory 18 normally outputs the H-level selection signal a, each of the selectors 198 to 21b receives signals from the internal memory 18 and the memory access circuit 17. Data bus 1 Address bus, write signal WR, and read signal RD are valid.

When the CPU 12 reads data from the external memory 16 via the memory access control device 15, an L level selection signal C8 is sent to the internal memory 18 via the decoder 23.
Sends 1. Thus, the internal memory 18 becomes operational. Thereafter, the CPU 12 transfers data to the internal memory 18 via the data bus 13a and the address bus 14a to the external memory 16.
For example, the control data such as the reading start number, read end address, etc. necessary for accessing is written.

When writing of control data is completed, memory access circuit 1
After confirming that the external memory 16 is operating the H-level ready signal READY, the address selectors 20 . External memory 16 via address bus 14b
A read address is specified in , and a read signal RD is applied to the external memory 16 via the signal selector 21b. The data stored at the corresponding address in the external memory 16 is transferred to the data bus 13. b. Read through the data selector 19b and write the read access data into the internal memory 18. In this manner, when the memory access circuit 17 completes the process of reading data under all conditions specified by the control data set in the internal memory 18, it sends the H-level ready signal READY from the internal memory 18 to the CPU 12.

When the CPU 12 receives the H level ready signal READY output from the internal memory 18, it outputs the L level read signal RD. In this state, the selection signal C82 input to the other terminal of the gate 22b is at H level, so the read signal RD is applied only to the internal memory 18. Then, the access data stored in the internal memory 18 is read via the data selector 19a and the data bus 13a.

The above is the operation of each part when reading data from the external memory 16 via the memory access control device 15, but the operation of each part when writing data to the external memory 16 via the memory access control device 15. Since the process also corresponds to the process when reading data, the explanation will be omitted.

Next, if some abnormality occurs and the CPU 12 needs to directly access the external memory 16, the CPU
12 writes control data to the internal memory 18 indicating that the bypass circuit is to be used. Then, the internal memory 18 inverts the level of the selection signal a from the H level to the L level. As a result, the second
terminals are connected to the common terminal. Therefore, the data bus 13a connected to the data terminal of the CPU 12 and the data bus 13b connected to the external memory 16 are directly connected via the data selectors 19a and 19b. Also, CPU
The address bus 14a connected to the 12 address terminals and the address bus 14b connected to the external memory 16 are directly connected via the address selector 20.

Then, when the CPU 12 outputs the L level selection signal C52 via the decoder 23, the gates 22a and 22b allow the write signal RD and read signal RD from the CPU 12 to pass through as they are. The write signal RD and read signal RD output from each gate 22a, 22b pass through each signal selector 21a, 21b, and are applied to the read terminal and write terminal of external memory 16. Further, the L level selection signal C82 inputs the ready signal READY signal output from the external memory 16 to the ready terminal of the CPU 12 via the gate 22d22e.

That is, within the memory access control device 15, the CPU 1
A bypass circuit 2 for directly accessing the external memory 16 is formed.

When such a bypass circuit is formed,
The CPU 12 can access data to the external memory 16 via this bypass circuit in exactly the same way as when accessing a normal memory.

In an information processing system in which the memory access control device 15 configured as described above is incorporated, if an abnormality occurs in the process in which the CPU 12 indirectly accesses the external memory 16 via the memory access control device 15, First, the CPU 2 starts with the memory access control/device 1.
5 in an operating state, a diagnostic program stored in, for example, another ROM is activated to investigate the location of the abnormality and analyze the cause of the abnormality. That is, control data for diagnosis is set in the internal memory 18, known data is written in the external memory 16 by the memory access circuit 17, and data at the same address is later read by the memory access circuit 17 and the internal It is stored in the memory 18.

Then, by reading the data in the internal memory 18 with the CPU 12 and comparing it with the written data,
Whether the abnormality is an abnormality in the external memory 16 itself, or whether the data bus including the memory access control device 15, address bus,
Determine whether each control line is abnormal.

If it is determined that the external memory 16 is normal through the above diagnostic processing, then similar diagnostic processing is performed using the bypass circuit. That is, the CPU 12 sends control data for use of the bypass circuit to the internal memory 18, outputs an L level selection signal CS2 via the decoder 23, and
The above-described bypass circuit is formed within the memory access control device 15. Then, a diagnostic program stored in another ROM or the like is activated to perform investigation processing to identify the location where the abnormality has occurred and analyze the cause of the abnormality.

In other words, known data is written to a pre-designated address in the external memory 16, and later the data stored in the corresponding address is read to determine whether the read data matches the written known data. investigate. If the result of running this diagnostic program is normal, it can be determined that some abnormality has occurred in the internal memory 18, memory access circuit 17, and other circuit members in the memory access control device 15.

In this way, by performing two diagnostic processes, the normal diagnostic process and the diagnostic process using the bypass circuit,
The location of the abnormality can be identified as: ■ Failure of the external memory 16 itself, ■ Failure of electronic components such as the internal memory 18 and memory access circuit 17 of the memory access control device 15, and ■ Failure of the external memory 15.
It is relatively easy to guess whether each bus or control line is at fault.

In this way, the CPU 12 is installed in the memory access control device 15.
By providing a bypass circuit for directly accessing the external memory 16, it is possible to easily guess whether the abnormality is occurring in the memory access control device 15 itself or other buses and control lines when an abnormality occurs. The cause can be determined in a short time. Further, even an operator who does not have particularly high technical knowledge regarding the memory access control device 15 can easily guess the location where an abnormality has occurred.

Moreover, there is no need to prepare a complicated diagnostic program, and a normal general-purpose diagnostic program can be used.

In addition, the fifth selectors 19a to 21b and the five gates 2
Since the bypass circuit is formed by simply adding very inexpensive circuit components such as 2a to 22e, manufacturing costs do not increase significantly compared to conventional memory access control devices.

Note that the present invention is not limited to the embodiments described above. For example, if the capacity of the internal memory 18 is small, the address bus 14 used in the memory access control device 15 may
If it is not possible to access all of the storage areas of the external memory 16 using only a, an address latch circuit 24 may be provided as shown in FIG. That is, by setting the missing address in advance in the address latch circuit 24 via the data bus 1.3a from the CPU 12, the set value of the address latch circuit 24 can be changed after the above-described diagnostic process is performed. By doing this, the external memory 16
Diagnostic processing can be executed across all storage areas of the system.

Furthermore, in the embodiment, a dual port RAM is used as the external memory 16, but in particular, a dual port RAM is used as the external memory 16.
It is not necessary to use AM, and the same effect can be obtained even when using normal ROM or RAM.

Furthermore, in the embodiment, the memory access control device 1
5, we used a gate array formed by a semi-custom LIS, but it is also possible to use a general AS including, for example, a full custom LSI.
It can also be fully applied to IC.

[Effects of the Invention] As described above, the memory access control device of the present invention is provided with a bypass circuit that bypasses the internal memory and the memory access circuit.

Therefore, if an abnormality occurs while the external control unit is indirectly accessing the external memory via this memory access control device, this bypass circuit is used to control the external memory such as the CPU. The unit can directly access the external memory, the location where the abnormality has occurred can be easily identified, and the abnormal state can be resolved in a short time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing main parts of an information processing system incorporating a memory access control device according to one embodiment of the present invention, and FIG. 2 is a block diagram showing main parts of a memory access control device according to another embodiment of the present invention. FIG. 3 is a block diagram showing main parts of an information processing system incorporating a conventional memory access control device. 12-CPU, 13a, 13b--data bus, 14
a, 14b...Address bus, 15...Memory access control device, 16...External memory, 17...Memory class circuit, 18...Internal memory, 19a19b
...Data selector, 2o...Address busk9.
218.21b...Signal selector, 23...Decoder. Applicant's agent Patent attorney Takehiko Suzue

Claims (1)

[Claims] The memory access circuit includes an internal memory and a memory access circuit, and the memory access circuit controls data access to an external memory connected to the outside based on control data set in the internal memory from an external control unit. and stores the obtained access data in the internal memory, and after the access data is stored in the internal memory, the external control unit executes data access to the internal memory. a bypass circuit for a control unit to directly access data from the external memory without going through the external memory and a memory access circuit; A memory access control device comprising a selection circuit that switches and connects from the circuit side to the bypass circuit side.