JPH0488632A - Formation of protective film for heat treatment - Google Patents

Formation of protective film for heat treatment

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Publication number
JPH0488632A
JPH0488632A JP20436990A JP20436990A JPH0488632A JP H0488632 A JPH0488632 A JP H0488632A JP 20436990 A JP20436990 A JP 20436990A JP 20436990 A JP20436990 A JP 20436990A JP H0488632 A JPH0488632 A JP H0488632A
Authority
JP
Japan
Prior art keywords
film
ammonia
monosilane
silicon nitride
films
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP20436990A
Other languages
Japanese (ja)
Other versions
JP2581281B2 (en
Inventor
Kiyotaka Benzaki
辨崎 清隆
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to JP2204369A priority Critical patent/JP2581281B2/en
Publication of JPH0488632A publication Critical patent/JPH0488632A/en
Application granted granted Critical
Publication of JP2581281B2 publication Critical patent/JP2581281B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To minimize the pinhole formation even if silicon nitride films are thinly formed by a method wherein the silicon nitride films whereon the compression inner stress is imposed are formed by controlling the specific flow rate of monosilane and ammonia as a reaction gas. CONSTITUTION:After the formation of an active layer on the surface of a semiconductor GaAs substrate 1, the surface oxide film is removed. Next, in order to form SiNX films 2 used as protective films for heat treatment, the GaAs substrate 1 is set on a heating base 7 inside the reaction chamber 6 of a plasma CVD device while a gas (alpha) comprising monosilane and ammonia is fed into a plasma CVD device 3 to flow along the surface of the substrate 1 which is supplied with high-frequency output power for depositing the SiNX films 2. Through these procedures, the SiNX films 2 contains the compression inner stress, and the inner stress can be reduced.

Description

【発明の詳細な説明】 口産業上の利用分野コ 本発明は、半導体装置の製造工程において用いられる熱
処理時保護用の形成方法に関する。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for forming protection during heat treatment used in the manufacturing process of semiconductor devices.

[背景技術] 化合物半導体装1等の製造工程においては、種々の熱処
理が行なわれる。例えば、イオン注入後には、注入され
たイオンがドナーやアクセプタとして働くようにするた
めに活性化アニールが行なわれる。
[Background Art] Various heat treatments are performed in the manufacturing process of the compound semiconductor device 1 and the like. For example, after ion implantation, activation annealing is performed so that the implanted ions function as donors and acceptors.

GaAs素子、AQGaAs素子、[nP素子等の化合
物半導体素子の製造工程においても、活性化アニールが
行なわれているが、これは比較的高温(800〜900
℃)で行なわれるので、蒸気圧の高いAs原子やP原子
が飛び出すことによって化合物半導体基板の表面の分解
や変質が起こり、素子特性を著しく悪化させる。
Activation annealing is also performed in the manufacturing process of compound semiconductor devices such as GaAs devices, AQGaAs devices, [nP devices, etc., but this is done at relatively high temperatures (800 to 900
C), As atoms and P atoms with high vapor pressure fly out, causing decomposition and alteration of the surface of the compound semiconductor substrate, significantly deteriorating device characteristics.

このため、従来にあっては、第3図(、a)に示すよう
に、半絶縁性GaAs基板1の表面にSiイオン4を注
入してGaAs基板l基板面にイオン注入領域5を形成
した後、第3図(b)に示すように、イオン注入領域5
をもつGaAs基板1の表面にスパッタ法やCVD法’
t: ヨ’) Si、N、膜10を1000〜2000
人程度の厚みに成膜していた。
For this reason, conventionally, as shown in FIG. 3(a), Si ions 4 are implanted into the surface of a semi-insulating GaAs substrate 1 to form an ion implantation region 5 on the surface of the GaAs substrate 1. After that, as shown in FIG. 3(b), the ion implantation region 5 is
Sputtering method or CVD method is applied to the surface of GaAs substrate 1 with
t: Yo') Si, N, film 10 from 1000 to 2000
The film had been formed to a thickness comparable to that of a human body.

口発明が解決しようとする課題] しかしながら、活性化アニールを施された半絶縁性Ga
As基板の結晶性や電気的特性は、この5iaN4膜の
膜厚や膜質に大きく依存している。例えば、膜厚を17
00Å以上に厚くすると、5iJ4膜の熱処理時におけ
る熱膨張のため半絶縁性GaAs基板に亀裂を生じるこ
とがあり、逆に、Si、N4膜の膜厚を1000Å以下
に薄くすると、Si、N、膜にピンホールが多数発生す
るという欠点があった。
[Problems to be Solved by the Invention] However, semi-insulating Ga that has been subjected to activation annealing
The crystallinity and electrical characteristics of the As substrate largely depend on the thickness and quality of this 5iaN4 film. For example, if the film thickness is 17
If the thickness of the Si, N4 film is reduced to 1000 Å or more, cracks may occur in the semi-insulating GaAs substrate due to thermal expansion during heat treatment of the 5iJ4 film. The drawback was that many pinholes were generated in the film.

このため、S!sNn膜としてはできるだけ薄く、より
緻密な膜を形成するのが好ましいが、あまり緻密なSi
3N、膜を形成すると、その引張内部応力が約L O1
lcfyne/ cm ”程度とかなり大きな引張力と
なる。この結果、5isN4膜の引張内部応力によって
GaAs基板結晶に結晶欠陥が生じやすくなり、製作さ
れた半導体素子の信頼性が低下するという問題があった
For this reason, S! It is preferable to form a thinner and denser sNn film as possible;
3N, when the film is formed, its tensile internal stress is about L O1
The tensile force is quite large, on the order of "lcfyne/cm".As a result, the tensile internal stress of the 5isN4 film tends to cause crystal defects in the GaAs substrate crystal, which poses a problem in that the reliability of the manufactured semiconductor device decreases. .

本発明は、叙上の従来例の欠点に鑑みてなされたもので
あり、その目的とするところは、厚みを薄くしてもピン
ホールが発生しにくく、また基板結晶に結晶欠陥を生じ
させにくい熱処理時保護用の形成方法を提供することに
ある。
The present invention has been made in view of the drawbacks of the conventional examples described above, and its purpose is to prevent pinholes from occurring even when the thickness is reduced, and to prevent crystal defects from forming in the substrate crystal. An object of the present invention is to provide a method for forming protection during heat treatment.

口課題を解決するための手段] このため、本発明の熱処理時保護用の形成方法は、プラ
ズマCVD法によって半導体基板の表fに熱処理時保護
用の窒化シリコン膜を形成する方法であって、モノシラ
ン及びアンモニアを反応ガスとし、モノシラン及びアン
モニアの流量比を制御することにより、圧縮内部応力を
有する窒化シリコン膜を成膜することを特徴としている
Means for Solving the Problem] Therefore, the method of forming a protection layer during heat treatment of the present invention is a method of forming a silicon nitride film for protection during heat treatment on the surface f of a semiconductor substrate by plasma CVD method, The method is characterized in that a silicon nitride film having compressive internal stress is formed by using monosilane and ammonia as reaction gases and controlling the flow rate ratio of monosilane and ammonia.

[作用コ プラズマCVD法に用いる反応ガスとしてモノシラン(
5LH4)及びアンモニア(NHs)を用い、モノシラ
ンとアンモニアの流量比を変化させた(特に、5tH4
/NHsのガス流量比を減少させてい)た)ところ、成
膜された窒化シリコン(SiNり膜の引張内部応力が減
少してゆき、ついには圧縮内部応力となった。したがっ
て、モノシランとアンモニアの流量比を制御することに
より、プラズマCVD法によって圧縮内部応力をもつ窒
化シリコン膜を形成することができる。
[Monosilane (
5LH4) and ammonia (NHs), and the flow rate ratio of monosilane and ammonia was varied (especially, 5tH4) and ammonia (NHs) were used.
As a result, the tensile internal stress of the deposited silicon nitride (SiN) film decreased and finally became compressive internal stress. By controlling the flow rate ratio, a silicon nitride film having compressive internal stress can be formed by plasma CVD.

この窒化シリコン膜は、圧縮内部応力をもつため、その
膜厚を例えば100OA程度に薄くしても、ピンホール
が発生しにくい。また、窒化シリコン膜の圧縮内部応力
は、従来より用いられている引張内部応力をもつ窒化シ
リコン膜と比較して応力の値が非常に小さいので、半導
体基板結晶の表面に窒化シリコン膜を形成しても結晶欠
陥が生じにくい。
Since this silicon nitride film has compressive internal stress, pinholes are unlikely to occur even if the film thickness is reduced to, for example, about 100 OA. In addition, the compressive internal stress of a silicon nitride film is extremely small compared to the conventionally used silicon nitride film with tensile internal stress, so it is possible to form a silicon nitride film on the surface of a semiconductor substrate crystal. However, crystal defects are less likely to occur.

[実施例コ 以下、本発明の実施例を添付図に基づいて詳述する。[Example code] Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

半絶縁性QaAs基板1は、イオン注入等により表面に
活性層(イオン注入領域5)を形成された後、表面の酸
化膜(図示せず)を除去される。この酸化膜除去工程は
、トリクロロエタン、アセトン等の溶剤を用いてGaA
s基板1の表面を有機洗浄した後、さらに塩酸(HCQ
)を用いて室温で数分間酸化膜のエツチングを行ない、
GaAs基板1の表面を清浄に整えるものである。つぎ
に、熱処理時保護用として用いられるSiNx膜(窒化
シリコン膜。Xは、窒素の組成比を示す。)2を成膜す
るため、第1図に示すように、プラズマCVD装置3の
反応室e内の加熱台7の上にGaAs基板1をセットし
、GaAs基板1の表面に沿って反応ガスαが流れるよ
う、プラズマCVD装置S内にモノシラン(Sit(4
)及びアンモニア(N)I3)からなる反応ガスαを供
給し、GaAs基板1の表面に約0 、2 W /cm
 2の高周波出力パワーを印加し、膜厚が1000人と
なるようにSiN、膜2を成長させる。
After an active layer (ion implantation region 5) is formed on the surface of the semi-insulating QaAs substrate 1 by ion implantation or the like, an oxide film (not shown) on the surface is removed. This oxide film removal process uses a solvent such as trichloroethane or acetone to remove the GaA
After organically cleaning the surface of the s-substrate 1, hydrochloric acid (HCQ)
) to etch the oxide film for several minutes at room temperature.
This cleans and prepares the surface of the GaAs substrate 1. Next, in order to form a SiNx film (silicon nitride film. The GaAs substrate 1 is set on the heating table 7 in the plasma CVD apparatus S, and monosilane (Sit (4
) and ammonia (N)I3) is supplied to the surface of the GaAs substrate 1 at a rate of about 0.2 W/cm.
A high frequency output power of 2 is applied to grow SiN film 2 to a thickness of 1000 nm.

ここで、プラズマCVD装置S内におけるGaAs基板
1の温度T、、、l、が300℃及び350℃の場合に
ついて、モノシラン及びアンモニアのガス流量比を変化
させ、成膜されたSUN、膜2の内部応力を測定したと
ころ、第2図のような結果を得た。
Here, when the temperature T,...l, of the GaAs substrate 1 in the plasma CVD apparatus S is 300°C and 350°C, the gas flow ratio of monosilane and ammonia is changed, and the When the internal stress was measured, the results shown in Figure 2 were obtained.

第2図の横軸はモノシラン/アンモニアの流量比を示し
ており、縦軸はSiN、膜2の内部応力を示し、上方が
圧縮内部応力、下方が引張内部応力となっている。すな
わち、モノシラン/アンモニアの流量比を減少させてい
くと、引張内部応力が減少する傾向を示し、ついには、
基板温度T a u bが300℃の場合には、モノシ
ラン/アンモニアの流量比が0.1’85の時に引張内
部応力から圧縮内部応力へ変化し、また、基板温度T、
ul、が350℃の場合には、モノシラン/アンモニア
の流量比が約0.16の時に引張内部応力から圧縮内部
応力へ変化した。しかも、従来のSiNx膜2では、引
張内部応力が約10 gdyne/ cm 2であった
のに対し、本発明によれば圧縮内部心力はほぼ均一な値
を示し、約10 ”dyne/ cm 2となった。
The horizontal axis of FIG. 2 shows the flow rate ratio of monosilane/ammonia, and the vertical axis shows the internal stress of SiN and the film 2, with the upper part being the compressive internal stress and the lower part being the tensile internal stress. In other words, as the monosilane/ammonia flow rate ratio decreases, the tensile internal stress tends to decrease, and eventually,
When the substrate temperature T a u b is 300°C, the tensile internal stress changes to the compressive internal stress when the monosilane/ammonia flow rate ratio is 0.1'85, and the substrate temperature T,
When ul was 350° C., the tensile internal stress changed to compressive internal stress when the monosilane/ammonia flow rate ratio was about 0.16. Moreover, in the conventional SiNx film 2, the tensile internal stress was approximately 10 gdyne/cm 2 , whereas according to the present invention, the compressive internal stress is approximately uniform, and is approximately 10” dyne/cm 2 . became.

そこで、基板温度T、、、が300℃の場合には、反2
ガスのモノシラン:アンモニアの流量比を約0.1 :
 1〜0.185:1となるように調整し、反応室6内
のガス圧を0.8〜1 torr、高周波出力パワーを
約0.2W/am2とし、100OA程度の厚みのSi
N工膜2を成膜した。あるいは、基板温度T * u 
bが350℃の場合には、度広ガスのモノシラン:アン
モニアの流量比を約0.1 : 1〜0゜1θO:1と
し、反応室のガス圧を0.8〜ttorr1高周波出力
パワーを約0.2W/cm”とし、膜厚が1000A程
度となるようにSiNx膜2を成膜した。
Therefore, when the substrate temperature T, , is 300°C,
The flow rate ratio of gas monosilane:ammonia is approximately 0.1:
1 to 0.185:1, the gas pressure in the reaction chamber 6 was set to 0.8 to 1 torr, the high frequency output power was set to about 0.2 W/am2, and the Si
A N coating film 2 was formed. Alternatively, the substrate temperature T*u
When b is 350°C, the flow rate ratio of monosilane:ammonia as diluent gas is set to approximately 0.1:1~0°1θO:1, and the gas pressure in the reaction chamber is set to 0.8~ttorr1.The high frequency output power is set to approximately 0.2 W/cm'', and the SiNx film 2 was formed to have a film thickness of about 1000 Å.

このようにして形成されたS iNx膜2は、圧縮内部
応力を有し、しかも約10 gdyne/ cm ”と
いう小さな値を示し、従来のS iN x膜の引張内部
応力が約1011dyne/ cm ”であったのと比
較すると、約1/10以下の値となり、内部心力を非常
に低減させることができた。SiN、膜2は、圧縮応力
をもっているため引き伸ばされておらず、1ooo人程
度に薄(してもピンホールが発生せず、良質の熱処理時
保護用を得ることができた。また、内部応力を小さな値
に低減させることができたので、SiNx膜2を形成さ
れているGaAs基板結晶に結晶欠陥が発生しにくくな
り、製造された素子の信頼性を向上させることができた
The SiNx film 2 thus formed has a compressive internal stress, which is as small as about 10 gdyne/cm'', while the tensile internal stress of the conventional SiNx film is about 1011 dyne/cm''. Compared to the previous case, the value was about 1/10 or less, and we were able to significantly reduce internal mental force. The SiN film 2 has compressive stress, so it is not stretched and is as thin as 100 mm (even if it is thin, no pinholes are generated and a high-quality protective film during heat treatment can be obtained. Since it was possible to reduce the value to a small value, crystal defects were less likely to occur in the GaAs substrate crystal on which the SiNx film 2 was formed, and the reliability of the manufactured device could be improved.

なお、上記実施例においては、GaAs基板の場合につ
いて説明したが、これ以外の■−v族化合物半導体素子
やシリコン系半導体素子等にも本発明を実施することが
できることはもちろんである。
Although the above embodiments have been described with reference to the case of a GaAs substrate, it goes without saying that the present invention can also be implemented in other types of semiconductor devices, such as Ⅰ-V group compound semiconductor devices, silicon-based semiconductor devices, and the like.

[発明の効果コ 本発明によれば、熱処理用の保護膜として用いられる窒
化シリコン膜の内部応力を圧縮応力とすることができる
ので、窒化シリコン膜の膜厚を例えば1000A程度に
薄くしてもピンホールが発生しなくなる。また、窒化シ
リコン膜の膜厚を薄くでき、しかも内部応力の値も小さ
くなるので、窒化シリコン膜の下の基板結晶に結晶欠陥
が発生しにくくなる。したがって、信頼性の高い半導体
素子(例えば、オーミック特性の良好な化合物半導体素
子)を製造することができる。
[Effects of the Invention] According to the present invention, the internal stress of the silicon nitride film used as a protective film for heat treatment can be made into compressive stress. Pinholes will no longer occur. Further, since the thickness of the silicon nitride film can be reduced and the value of internal stress is also reduced, crystal defects are less likely to occur in the substrate crystal under the silicon nitride film. Therefore, a highly reliable semiconductor device (for example, a compound semiconductor device with good ohmic characteristics) can be manufactured.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を示す概略図、第2図はモノ
シラン/アンモニアのガス流量比と窒化シリコン膜の内
部応力との関係を示す図、第3図(a) (b)は従来
例を説明する断面図である。 1・・・GaAs基板 2・・・窒化シリコン膜 3・・・プラズマCVD装置 α・・・反応ガス 特許出願人 株式会社 村田製作所 代理人  弁理士 中 野 雅 房
Figure 1 is a schematic diagram showing an embodiment of the present invention, Figure 2 is a diagram showing the relationship between the monosilane/ammonia gas flow rate ratio and the internal stress of the silicon nitride film, and Figures 3 (a) and (b) are FIG. 2 is a sectional view illustrating a conventional example. 1...GaAs substrate 2...Silicon nitride film 3...Plasma CVD device α...Reactive gas Patent applicant Murata Manufacturing Co., Ltd. Representative Patent attorney Masafusa Nakano

Claims (1)

【特許請求の範囲】[Claims] (1)プラズマCVD法によって半導体基板の表面に熱
処理時保護用の窒化シリコン膜を形成する方法であって
、 モノシラン及びアンモニアを反応ガスとし、モノシラン
及びアンモニアの流量比を制御することにより、圧縮内
部応力を有する窒化シリコン膜を成膜することを特徴と
する熱処理用保護膜の形成方法。
(1) A method of forming a silicon nitride film for protection during heat treatment on the surface of a semiconductor substrate by plasma CVD method, in which monosilane and ammonia are used as reaction gases, and by controlling the flow rate ratio of monosilane and ammonia, A method for forming a protective film for heat treatment, characterized by forming a silicon nitride film having stress.
JP2204369A 1990-07-31 1990-07-31 Method for manufacturing compound semiconductor device Expired - Lifetime JP2581281B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2204369A JP2581281B2 (en) 1990-07-31 1990-07-31 Method for manufacturing compound semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2204369A JP2581281B2 (en) 1990-07-31 1990-07-31 Method for manufacturing compound semiconductor device

Publications (2)

Publication Number Publication Date
JPH0488632A true JPH0488632A (en) 1992-03-23
JP2581281B2 JP2581281B2 (en) 1997-02-12

Family

ID=16489376

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2204369A Expired - Lifetime JP2581281B2 (en) 1990-07-31 1990-07-31 Method for manufacturing compound semiconductor device

Country Status (1)

Country Link
JP (1) JP2581281B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017108077A (en) * 2015-12-11 2017-06-15 旭化成エレクトロニクス株式会社 Hall sensor and manufacturing method thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61284928A (en) * 1985-06-10 1986-12-15 Mitsubishi Electric Corp Semiconductor device
JPS62287645A (en) * 1986-06-06 1987-12-14 Nec Corp Semiconductor integrated circuit
JPS6315426A (en) * 1986-07-08 1988-01-22 Sanyo Electric Co Ltd Semiconductor device
JPS63132433A (en) * 1986-11-21 1988-06-04 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61284928A (en) * 1985-06-10 1986-12-15 Mitsubishi Electric Corp Semiconductor device
JPS62287645A (en) * 1986-06-06 1987-12-14 Nec Corp Semiconductor integrated circuit
JPS6315426A (en) * 1986-07-08 1988-01-22 Sanyo Electric Co Ltd Semiconductor device
JPS63132433A (en) * 1986-11-21 1988-06-04 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017108077A (en) * 2015-12-11 2017-06-15 旭化成エレクトロニクス株式会社 Hall sensor and manufacturing method thereof

Also Published As

Publication number Publication date
JP2581281B2 (en) 1997-02-12

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