JPH0492477A - Manufacture of variable capacity diode - Google Patents

Abstract

PURPOSE:To reduce characteristic irregularity of a variable capacity diode by forming an impurity concentration distribution by ion implanting of excellent controllability and annealing at a low temperature for a short time. CONSTITUTION:With photoresist mask 7 to be used as a mask, P is ion implanted in the opening of the photoresist mask 5.5X10<11>/cm<2> at 250keV. Further, after the mask 7 is removed, it is covered with other photoresist mask 8. With the mask 8 to be used as a mask P is ion implanted in the opening of the mask 4.5X10<11>/cm<2> at 36OkeV, then annealed at a low temperature of 900 deg.C for a short time of 20sec by a lamp annealing unit to distribute the P, thereby forming an impurity concentration distribution having a p-n junction of a variable capacity diode. Thus, an irregularity in the diffusing depth of the impurities by heat treating is reduced, and characteristic irregularity in the diode can be reduced.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a technology that is effective when applied to semiconductor manufacturing technology, for example, a technology that is particularly effective when applied to variable capacitance diode manufacturing technology. It is.

[Conventional technology] The driving voltage for variable capacitance diodes is becoming lower, and the frequency band that should be covered by variable capacitance diodes is becoming broader. There has been a need for variable capacitance diodes with good capacitance characteristics.

By the way, conventional manufacturing techniques for variable capacitance diodes are disclosed in Japanese Patent Application Laid-open Nos. 55-156373 and 1982-133.
No. 578, JP-A-55-29169, JP-A-47-1
No. 8283, JP-A-56-78174, JP-A-49-5
1879, Japanese Patent Publication No. 41-11054, and the like are known.

In this first category-〇 technology, an n-type epitaxial layer is formed on an n-type semiconductor substrate, n-type impurity ions are implanted into specific regions of the epitaxial layer, and heat treatment is performed at high temperature and for a long time several times. A variable capacitance diode is manufactured by forming an n+ super-step layer by repeating the steps, and then forming a p+ n+ junction by ion implantation of p-type impurity at a high concentration and heat treatment at high temperature for a long time.

Further, as another technique (second category technique), for example, the technique described in Japanese Patent Publication No. 56-26477 is known.

In this technology, an n-type epitaxial layer of approximately IXIO''/cffl is formed on a highly doped substrate of approximately 1×10''/cf, and a p-type impurity is first doped into a limited portion of this epitaxial layer. Ion implantation, 900℃, 20
Next, n-type impurities were ion-implanted several times at different energies and doses at 800°C.
A variable capacitance diode is manufactured by forming a p+-〇+ junction by heat treatment for 20 minutes.

[Problems to be Solved by the Invention] However, in the technology of the first category, the impurity concentration distribution is formed by multiple ion implantations and heat treatment at high temperature for a long time, so that the impurity concentration distribution required in the shallow region is Not only is it impossible to form an impurity distribution, making it impossible to form a variable capacitance diode with a high capacitance change ratio and good linearity, but there are also problems in that the characteristics vary widely due to thermal diffusion and the diffusion process takes a long time.

On the other hand, in the technique of the second category mentioned above, the method of forming a pn junction with B (boron) does not take into account the channeling phenomenon during boron ion implantation, and furthermore, Since the impurity having a large coefficient is ion-implanted first, there is a problem in that it is difficult to form a shallow impurity layer with a desired impurity concentration.

There is also the problem that an impurity concentration distribution cannot be efficiently formed in the depth direction.

As a technology to solve the problem of this latter category of technology, in which the junction depth of impurities becomes deeper due to channeling of impurities, we have developed a technology that uses atoms with an atomic radius equal to or greater than that of the atoms constituting the semiconductor substrate. (Si, Ge, Ar, etc.)
A method has been reported in which ions are implanted in advance to make the surface layer of a semiconductor substrate amorphous. It has also been reported that the formation of a p-type impurity layer using B can also be achieved by implanting high molecular weight ions such as BP. These reports can be found in Monthly Semiconductor World 2 (1986)
Discussed on pages 67-73.

However, among methods for suppressing channeling in this technology, in the case of Ar or BF ion implantation, there is a problem that junction leakage current increases due to lattice defects caused by the presence of atoms unrelated to electrical characteristics. , Si
In the case of implantation, channeling cannot be completely prevented, resulting in a pn junction having a gentle shape. Therefore, there is a problem that the capacitance value at low bias of the capacitance-voltage characteristic decreases, and the capacitance change ratio cannot be increased.

The present invention has been made in view of these points, and aims to reduce the variation in capacity-voltage characteristics and reduce the number of steps in the diffusion process. Another object of the present invention is to provide a method for manufacturing a variable capacitance diode having a large capacitance change ratio and excellent linear capacitance-voltage characteristics.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

The invention according to claim 1 includes ion implantation of p-type impurities;
When manufacturing a variable capacitance diode through multiple ion implantation of n-type impurities and annealing, ion implantation of n-type impurities with an atomic radius equal to or greater than that of the atoms constituting the semiconductor substrate is performed to make the region amorphous. After that, n
In this method, ion implantation of a type impurity is performed, followed by low-temperature, short-time annealing, followed by multiple ion implantation of n-type impurities, followed by low-temperature, short-time annealing.

The invention according to claim 2 is the invention according to claim 1,
In ion implantation of impurities, impurities with smaller diffusion coefficients are ion-implanted earlier.

The invention according to claim 3 is the invention according to claim 1, in which after As ion implantation is performed to make the region amorphous, B ion implantation is performed, and then low temperature
Short-time annealing is performed, multiple P ion implantation is performed, and then low-temperature, short-time annealing is performed.

[Function] According to the above-described means, the impurity concentration distribution is formed by ion implantation with good controllability and annealing at low temperature for a short time, so there is little variation in the diffusion depth of impurities due to heat treatment, and variable capacitance is achieved. Variations in diode characteristics can be reduced.

In addition, ion implantation of n-type impurities having an atomic radius equal to or greater than that of the atoms constituting the semiconductor substrate is performed, into the semiconductor substrate surface.
This makes the surface of the semiconductor substrate amorphous, which makes it possible to suppress channeling of impurity atoms that are subsequently ion-implanted, thereby making it possible to form an impurity layer with a desired depth. Furthermore, the n-type impurity that is ion-implanted for the purpose of making the surface of the semiconductor substrate amorphous is activated by anil, and the concentration distribution of the n-type impurity formed thereafter can be corrected. This improves the capacitance characteristics in the direction of increasing the capacitance change ratio.

Furthermore, in the method according to claim 2 or 3, in which the impurity having a smaller diffusion coefficient is ion-implanted earlier, the implanted impurity does not spread more than necessary, so that it is easy to achieve the desired impurity concentration in the depth direction. distribution can be formed.

[Example] Hereinafter, an example of the present invention will be described based on FIGS. 1, 2, and 3.

FIGS. 1A to 1H are cross-sectional views of the manufacturing process of a variable capacitance diode, and FIG. 2 shows the process flow. The manufacturing method of this variable capacitance diode is shown in Figure 1 (A).
The explanation will be as follows based on (H) to (H) and FIG.

First, as shown in FIG. 1(A), an n-type epitaxial layer 2 of approximately 2×10''/an? is formed on a highly doped n-type substrate 1.
form.

Next, as shown in FIG. 1(B), an oxide film 3 is deposited on the epitaxial layer 2.

Subsequently, a region of the oxide film 3 where a variable capacitance diode is to be formed is removed to form an opening, and then light oxidation is performed. As a result, a thin oxide film 3a is also formed in the opening of the oxide film 3. This thin oxide film 3a is formed in a dry O5 atmosphere at 900°C.

The thickness of this oxidized Jllj3a is approximately 300 layers, and functions as a protective film for the Si surface during ion implantation.

After that, a photoresist mask 4 is formed. This photoresist mask 4 has a pattern that hides the periphery of the opening of the oxide film 3 and the outer part thereof. Next, using the photoresist mask 4 as a mask, As is applied to the opening of the photoresist mask 4 at 190 keV and l.
Implantation is performed at X I O1/cm' to make the Sl surface layer amorphous, resulting in the state shown in FIG. 1(D).

Next, after removing the photoresist mask 4, another photoresist mask 5 is applied. The size of the opening O portion of this photoresist mask 5 is as follows.
The size of the opening is set to be slightly larger than that of the opening. Then, using this photoresist mask 5 as a mask, 35k of B was applied to the opening of the photoresist mask 4.
eV, 5 x 10"/Cm' implantation (Figure 1 (E))
, low-temperature, short-time annealing at 950°C for 20 seconds was performed using a lamp annealing device to form the shallow junction B in (a) of Figure 3(A), and at the same time activate As, resulting in the distribution of (b). form.

Next, after removing the photoresist mask 5, another photoresist mask 6 is applied. The size of the opening of this photoresist mask 6 is set to be slightly larger than the size of the opening of the photoresist mask 4. Then, using this photoresist mask 6 as a mask, 190 ke of P was applied to the opening of the photoresist mask.
Ion implantation is performed at V, 7.degree.

The size of the opening of this photoresist mask 7 is set to be slightly smaller than the size of the opening of the photoresist mask 6. Then, using this photoresist mask 7 as a mask, P was applied to the opening of the photoresist mask at 250 keV, 5.5×10”/cffl.
Ion implantation is performed using (Fig. 1 (G)). Further, after removing the photoresist mask 7, another photoresist mask 8 is applied. The size of the opening of this photoresist mask 8 is set to be slightly smaller than the size of the opening of the photoresist mask 7 described in I.

Then, using this photoresist mask 8 as a mask, P was applied to the opening of the photoresist mask at 360 keV, 4,
Ion implantation was performed using 5X 10"/cr'11 as shown in Figure 1 (
H)), then low-temperature, short-time annealing at 9.00°C for 20 seconds was carried out using a lamp annealing device, as shown in Figure 3 (
By forming the distribution of P in A) and (C),
D) An impurity concentration distribution having a pn junction of a variable capacitance diode is formed.

Thereafter, electrodes are formed, etc., and a variable capacitance diode is manufactured.

Incidentally, if the Si surface is not made amorphous by As implantation, the distribution of B will be as shown in (a) of Figure 3(B), as the bond will become deeper due to channeling during implantation, as shown in Figure 3(B). The impurity concentration distribution has a pn junction as shown in (d) of (B).

In addition, the capacitance characteristics consisting of the impurity concentration distribution shown in (d) of FIG. 3(A) and FIG. 3(B) are respectively
It will look like a and b in the figure. The capacitance characteristic a produced by the process shown in FIGS.
Compared to the case where the surface is not made amorphous, the capacitance value becomes larger near IV, and a higher capacitance change ratio can be obtained.

According to the above method, the following effects can be obtained.

First, the impurity concentration distribution is formed by well-controlled ion implantation and low-temperature, short-time annealing, so there is little variation in the impurity diffusion depth due to heat treatment, reducing variation in the characteristics of the variable capacitance diode. .

In addition, by ion-implanting the n-type impurity As, which has an atomic radius equal to or larger than that of the Si atoms constituting the semiconductor substrate, into the semiconductor substrate surface, the semiconductor substrate surface becomes amorphous, which makes it difficult for subsequent ion implantation. Impurity atoms B, P
channeling can be suppressed, thus making it possible to form an impurity layer with a desired depth. In addition, the n
The type impurity As is activated by annealing and can correct the n-type impurity concentration distribution formed thereafter.

This improves the capacitance characteristics in the direction of increasing the capacitance change ratio.

Furthermore, since impurities with smaller diffusion coefficients are ion-implanted earlier, the implanted impurities do not spread more than necessary, and a desired impurity concentration distribution can be easily formed in the depth direction.

Although the invention made by the present inventor (0) has been specifically explained based on examples, the present invention is not limited to the above-mentioned examples, and it should be noted that various changes can be made without departing from the gist of the invention. Not even.

In the above description, the invention made by the present inventor was mainly explained using as an example the manufacturing technology of variable capacitance diodes, which is the field of application behind the invention, but the invention can be applied to general semiconductor manufacturing technology that requires a shallow pn junction.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

That is, according to the present invention, since the impurity concentration distribution is formed by ion implantation with good controllability and annealing at low temperature for a short time, there is little variation in the diffusion depth of impurities due to heat treatment, and it is variable. Characteristic variations in capacitor diodes can be reduced.

In addition, by ion-implanting n-type impurities into the semiconductor substrate surface, which have an atomic radius equal to or greater than that of the atoms constituting the semiconductor substrate, the semiconductor substrate surface becomes amorphous, so that the impurity atoms that are subsequently ion-implanted become amorphous. channeling can be suppressed, thus making it possible to form an impurity layer with a desired depth. Furthermore, the n-type impurity that has been ion-implanted for the purpose of making the surface of the semiconductor substrate amorphous can be activated by anil, and the concentration distribution of the n-type impurity formed thereafter can be corrected. This improves the capacitance characteristics in the direction of increasing the capacitance change ratio.

Furthermore, in the method according to claim 2 or 3, in which the impurity having a smaller diffusion coefficient is ion-implanted earlier, the implanted impurity does not spread more than necessary, so that it is easy to achieve the desired impurity concentration in the depth direction. distribution can be formed.

[Brief explanation of drawings]

Fig. 1 is a vertical cross-sectional view of each step showing a manufacturing method according to an embodiment of the present invention, Fig. 2 is a process flow diagram showing a manufacturing method according to an embodiment of the present invention, and Fig. 3 (A,) is a Figure 2 is an impurity concentration distribution diagram formed by the manufacturing method shown in Figure 3 (B) is an impurity concentration distribution diagram formed by the conventional manufacturing method, Figure 4 is the conventional manufacturing method and the manufacturing method shown in Figure 2. This is the capacitance-voltage characteristic of a variable capacitance diode manufactured in 1... Semiconductor substrate, 2... Epitaxial layer. Figure 1 Figure 1 Figure Figure □D 1

Claims (1)

[Claims] 1. In manufacturing a variable capacitance diode through ion implantation of p-type impurities, multiple ion implantation of n-type impurities, and annealing, the atomic radius is equal to or greater than that of atoms constituting the semiconductor substrate. After ion implantation of n-type impurities to make the region amorphous, ion implantation of p-type impurities is performed, followed by low-temperature, short-time annealing,
Furthermore, the method for manufacturing a variable capacitance diode is characterized in that multiple ion implantation of n-type impurities is performed, followed by low-temperature, short-time annealing. 2. The method of manufacturing a variable capacitance diode according to claim 1, wherein in the ion implantation of impurities, impurities with smaller diffusion coefficients are ion-implanted earlier. 3. After performing As ion implantation to make the region amorphous, B ion implantation is performed, followed by low-temperature, short-time annealing, and multiple P ion implantation, followed by low-temperature, 3. The method of manufacturing a variable capacitance diode according to claim 1, wherein the annealing is performed for a short time.