JPH04264647A - Fault information storage circuit - Google Patents

Abstract

PURPOSE:To obtain sufficient fault information without storing multiple and the same fault information. CONSTITUTION:A parity error detection circuit 1 detects a parity error from a signal B and a signal C. A memory 5 stores the value of an address signal A with the output of a counter 4 as an address based on the detection of the parity error. A memory 6 stores the address signal A. Since the logic '0' of an AND gate 9 is inputted to the address signal A which is the same as the address which is previously stored in the memory 6, a storage operation for the memory 5 is not executed again.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fault information storage circuit in a digital data transfer circuit.

0002

[Prior Art] Generally, digital data transfer in an information processing device is performed from an address indicating a transfer destination, data as transfer information, a transfer clock as a transfer timing, and a parity bit line for data to detect a transfer failure. It is configured.

Furthermore, the digital data transfer circuit is provided with a failure information storage circuit for storing the failure address when a failure (parity error) occurs.

FIG. 3 shows an embodiment of a conventional failure information storage circuit in a digital data transfer circuit, and FIG. 4 is a waveform diagram for explaining the operation of the circuit shown in FIG.

In FIG. 3, 1 is a parity error detection circuit, 2 is an AND gate, 3 is a delay circuit, 4 is a counter,
5 is a memory.

Signal B is data, signal A is the address of signal B, signal C is the parity bit of signal B, and signal D is signal A.
and the transfer clock of signals B and C, and signal I is the transfer clock of counter 4.
This is the reset signal.

Signals A, B, and C are set so that the time when signal D changes from logic "0" to logic "1" is in the middle of the signal stable period.

The signal D has a logic “1” that is 1/1 of the period of the signal D.
This is a signal that becomes logic "0" after continuing for a time of 4.

The parity error detection circuit 1 is a circuit that detects a parity error from the signal B and the signal C. When a parity error is detected, the signal E is set to logic "1".

The delay circuit 3 converts the signal F into 1/1 of the period of the signal D.
It is output as signal G with a delay of 2 times.

The counter 4 adds 1 to the value of the signal H, which is the output signal of the counter 4, at the timing when the signal G changes from logic "0" to logic "1" (hereinafter referred to as rising edge).

When the signal I is set to logic "1", the counter 4 sets the value of the signal H to zero.

The memory 5 uses the signal H as a storage address,
Signal F is used as a storage control signal, and the value of address signal A at that time is stored as data at the address indicated by the value of signal H at the time when signal F changes from logic "0" → logic "1" → logic "0". do the action.

When no parity error occurs in data signal B, signal E is logic "0", so signal F, which is the output of AND gate 2, becomes logic "0" regardless of the logic of signal D. When signal F is logic “0”, memory 5
Since the storage control signal is at logic "0", nothing is stored in the memory 5.

Further, the signal G which is delayed from the signal F also has the logic "0".
”, the counter 4 does not perform an addition operation.

At point (■) in FIG. 4, when address signal A is X and a parity error occurs in data signal B, signal E becomes logic "1", so signal D becomes logic "1".
At this time, the signal F becomes logic "1".

At the timing when the signal F is logic "1", the memory 5 receives the signal H using the value X of the address signal A as data.
is stored at the address of the value.

After storing in the memory 5, the signal G rises, and the counter 4 performs an addition operation and adds 1 to the value of the signal H.

If a parity error occurs again in the data signal B when the address signal A is X at the time point (■) in FIG. 4, the memory 5 is
4, the value X of the address signal A is stored as data at an address that is one value larger than the value of the signal H at the time point (3) in FIG. In this way, the value of the address signal A corresponding to the data signal B in which a parity error has occurred can be stored in the memory 5. Since the value of signal H is updated when a parity error occurs, the data of address signal A at the time when a parity error occurs is stored in memory 5 without being overwritten at the same address in memory 5.

[0020]

However, in the circuit described above, when a parity error occurs at a certain address (for example, the value X of address signal A in FIG. 4),
Since the fault information is unconditionally stored in the fault information storage circuit each time it occurs (for example, at times ◯ and ◯ in FIG. 4), a large amount of the same fault information is stored in the fault information storage circuit.

[0021] If the fault information storage circuit becomes full with the same fault information, other fault information cannot be stored, so the stored fault information is not sufficient as information for maintenance. This problem arises.

The present invention has been made to solve the above-mentioned problems, and prevents the omission of other fault information due to the storage of a large number of the same fault information in the fault information storage circuit, and ensures sufficient maintenance during maintenance. An object of the present invention is to provide a fault information storage circuit that can obtain accurate fault information.

[0023]

[Means for Solving the Problems] A fault information storage circuit according to the present invention includes a detection means for detecting occurrence of a fault, a storage means for storing information regarding the fault, and information regarding the fault detected by the detection means is stored in the memory. The apparatus is provided with a determining means for determining whether or not the fault is stored in the means, and a means for causing the storing means to perform a storing operation only for the fault which the determining means determines is not stored.

[0024]

[Operation] According to the present invention, since the storage means performs the storage operation only for faults that are determined by the judgment means to have not been stored yet, the fault information for which the occurrence of a fault is detected for the first time is reliably stored; If the same stored fault occurs, it will not be stored twice.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a circuit diagram of a failure information storage circuit showing an embodiment of the present invention, and FIG. 2 is a waveform diagram for explaining the operation.

In FIG. 1, 1 is a parity error detection circuit, 2 is an AND gate, 3 is a delay circuit, 4 is a counter, and 5 is a parity error detection circuit.
is a memory, 6 is a memory, 7 is a delay circuit, 8 is an inverter, and 9 is an AND gate.

Signal B is data, signal A is the address of signal B, signal C is the parity bit of signal B, and signal D is signal A.
, a transfer clock for signals B and C, and signal I is a reset signal. Signal A, signal B, and signal C are based on the logic of signal D.
It is set so that the time point at which the signal changes from logic "0" to logic "1" is in the middle of the signal stable period.

The signal D has a logic “1” that is 1/1 of the period of the signal D.
This is a signal that becomes logic "0" after continuing for a time of 4.

The parity error detection circuit 1 is a circuit that detects a parity error from the signals B and C, and sets the signal E to logic "1" when a parity error is detected.

The delay circuit 3 changes the signal F to 1/1 of the period of the signal D.
It is output as signal G with a delay of 2 times.

The counter 4 adds 1 to the value of the signal H, which is the output signal of the counter 4, at the timing of the rising edge of the signal G.

When the signal I is set to logic "1", the counter 4 sets the value of the signal H to zero.

The memory 5 uses the signal H as a storage address,
An operation in which signal K is used as a storage control signal, and the value of address signal A at that time is stored as data at the address indicated by signal H at the time when signal K changes from logic "0" → logic "1" → logic "0". do.

The memory 6 uses the address signal A as a storage address and the signal L as a storage control signal.
0”, no storage operation is performed, and when the signal L is logic “1”, the value of signal A at that time is used as the address, and the logic “1” is stored.
” to remember. The memory 6 outputs the stored contents corresponding to the address of the signal A as a signal J.

Further, this circuit is initialized by first setting the reset signal I to logic "1", and all the stored contents of the memory 6 become logic "0". Therefore, the signal J becomes logic "1" for the address where the memory 6 storage operation was performed, and becomes logic "0" for all other addresses.

The delay circuit 7 converts the signal F into one period of the signal D.
It is output as signal L with a delay of /4 time.

Next, the operation of the circuit shown in FIG. 1 will be explained with reference to FIG.

First, when no parity error occurs in data signal B, signal E is logic "0", so
The output signals F and K of AND gates 2 and 9 are both logic "0"
Therefore, the counter 4 does not perform an addition operation, and the memory 5 does not perform a storage operation. Further, since the signal L is also logic "0", the memory 6 also does not perform a storage operation.

Next, at time (3), if a parity error occurs in the data signal B, the signal E becomes logic "1", and when the signal D is logic "1", the signal F becomes logic "1".

The value X of the signal A is input to the address of the memory 6, but since the stored content of the memory 6 at this address X is a logic "0", the output signal J is a logic "0".
0".

The logic "0" of this signal J becomes logic "1" at the inverter 8, and is input as the signal M to the AND gate 9.

The output signal K of the AND gate 9 becomes logic "1" when the signal F is logic "1", and at that time, the output signal K of the AND gate 9 becomes logic "1".
stores the value X of the address signal A as data at the address indicated by the signal H.

After storing in the memory 5, the counter 4 performs an addition operation at the rising edge of the signal G and adds 1 to the value of the signal H.

When the output signal L of the delay circuit 7 becomes a logic "1", the memory 6 outputs a logic "1" to the address X indicated by the signal A.
” to remember.

Next, at point (3), when the value of address signal A is X again, if a parity error occurs in data signal B, signal E becomes logic "1" and signal D becomes logic "1". At times, the signal F also becomes logic "1".

The value X of the signal A is input to the address of the memory 6, but since the logic "1" was stored in the address X of the memory 6 at the previous time, the output signal J is the logic "1". 1”.

Since the output signal M of the inverter 8 is a logic "0", the output signal K of the AND gate 9 also becomes a logic "0", and the memory 5 does not perform a storage operation. Further, the counter 4 also does not perform an addition operation.

Note that when the signal L becomes the logic "1", the logic "1" is stored in the address X of the memory 6 again.

In this way, only the address signal A corresponding to the first parity error signal B is stored in the memory 5, and the second and subsequent parity errors of the same address signal A are not stored. Further, since the value of the signal H is updated only when it is stored in the memory 5, it is stored at the same address in the memory 5 without being overwritten.

[0050]

[Effects of the Invention] As explained above, according to the present invention, since the same fault information is not stored in the fault memory circuit more than once, the situation where fault information is missing even if many faults occur is avoided. can be avoided and sufficient failure information can be obtained during maintenance.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a fault information storage circuit of the present invention.

FIG. 2 is a waveform diagram illustrating the operation of the fault information storage circuit of the present invention.

FIG. 3 is a circuit diagram showing a conventional failure information storage circuit.

FIG. 4 is a waveform diagram illustrating the operation of a conventional failure information storage circuit.

[Explanation of symbols]

1 Parity error detection circuit 2,9 AND gate 3,7 Delay circuit 4 Counter 5,6 Memory 8 Inverter

Claims (1)

[Claims] 1. Detecting means for detecting the occurrence of a fault, storage means for storing information regarding the fault, and determining means for determining whether information regarding the fault detected by the detecting means is stored in the storage means. and only for the faults that are determined by the determining means to not be stored,
A fault information storage circuit comprising: means for causing the storage means to perform a storage operation.