JPH0498687A - output buffer circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a technology that is effective when applied to an output buffer circuit, and furthermore, a tri-state output buffer circuit having a level conversion function.
This article relates to techniques that are effective for use in RAM data output buffer circuits.

[Prior Art] For example, in an SRAM, a tri-state output buffer circuit having a level conversion function is used to convert stored data read by a sense amplifier to a predetermined logic level and output it to an external bus. (For example, Nikkei B
Published by P Company “Nikkei Electronics December 29, 1986
Day number (no.

410) J129-146, see explanation).

FIG. 11 shows an example of the configuration of the output buffer circuit.

The output buffer circuit shown in the figure is a B1C03M high-speed S
This was studied by the present inventors for use in the output section of storage read data in a RAM, and its main parts are first and second levels for converting the levels of logic input signals +Lin and -Lin. Conversion circuit 1.2 and outputs 11.2 of the first and second level conversion circuits 1 and 2
1, and a tri-state circuit that switches the state of the output 31 in this output circuit 3 to a binary power state of H (high level) and L (low level) or a high impedance state. It is constituted by a control circuit 5.

The level conversion circuits 1 and 2 are connected to the power supply potential VCC and have mutually complementary logic input signal terminals Lin, -.
The first and second p-channel MOS transistors Mpl, Mp2 are on/off controlled by Lin, and the source current Im of the second MOS transistor Mp2 is controlled by the source current Imi of the first MOS transistor Mpl.
The second
A level-converted output is taken out from the source side of the MOS transistor Mp2 and given to the output element of the output circuit section 3 as a drive signal.

The output circuit section 3 has a bipolar transistor Q1 for pull-up drive, a bipolar transistor Q2 for level shift, and an n-channel MOS transistor Mnl for pull-down drive connected in series between a power supply potential Vcc and a reference potential. Ql-G2
An output 31 is derived from an intermediate connection point between and Mnl, a so-called node. Ql and Mnl are controlled on/off in a complementary manner by the outputs 11 and 21 of the level conversion circuits 1 and 2, so that a logic signal Lout of a predetermined level is outputted to the output 31. .

The tri-state control circuit 5 includes the level conversion circuit 1.
It is constructed by interposing logic gates (OR logic) G1 and G2 at the front stage of 2.

Here, when the level conversion circuit control signal Cin is L, the logic input signals +Lin and -Lin are the logic gates Gl and G2.
is transmitted and input to tristates 1 and 2. As a result, the 31 outputs become in a binary output state which assumes a logic level of either H or L depending on the logic state of the logic input signals +Lin and -Lin.

On the other hand, when the control signal C1n7!1l (H), the logic inputs of the level conversion circuits 1 and 2 are the logic gates Gl.

Due to the logic operation of G2, the logic input signal +Lin.

-Both are fixed to H regardless of the state of Lin.

As a result, both Ql and Mnl of the output circuit section 3 are turned off, and the output 31 receives the logic input signals +Lin and -Li.
Regardless of the state of n, it is in a high impedance state.

As described above, the level conversion circuit operates so that the output 31 takes either the H, L, or high impedance state.

FIG. 12 shows another example of the configuration of the output buffer circuit.

The output buffer circuit shown in the figure was also studied by the present inventors. To explain the differences from the one shown in FIG. 12, this output buffer circuit has 1. Tri-state control circuit 5 is constructed by interposing p-channel MOS transistors Mp3 in series between power supply potential Vcc and level conversion circuit 1.2.

Here, when the MOS transistor Mp3 of the tri-state control circuit 5 is in the on state due to the control signal Cin, the level conversion circuits 1 and 2 are connected to the power supply potential V
cc, Ql and M of the output circuit section 3
nl are driven on/off in a complementary manner. As a result, the output 31 becomes a binary power state in which it outputs either H or L depending on the logic states of the logic input signal children Lin and -Lin.

On the other hand, when Mp3 is turned off by setting Cin to H, the level conversion circuits 1 and 2 switch to the power supply potential Vc.
By being disconnected from c, both Ql and Mnl are turned off. This causes the output 31 to become the logic input signal +
Regardless of the states of Lin and -Lin, it becomes a high impedance state.

As described above, a tristate operation is performed in which the output takes either the H, L, or high impedance state.

[Problems to be Solved by the Invention] However, the inventors have found that the above-mentioned technique has the following problems.

That is, in the circuit shown in FIG. 11, the logic gate Gl constituting the tristate control circuit 5.

Since G2 is interposed as a delay element in the transmission path of the logic input signals +Lin, -Lin and the control signal Cin, the transmission speed of the signals +Lin, -Lin and the control signal Cin are
There was a problem in that the response of the tri-state control was slow.

In the circuit shown in FIG. 12, immediately after switching the MOS transistor Mp3 of the tri-state control circuit 5 from off to on, the p-channel MOS transistor Mpl of the level conversion circuit 1.2 is switched on.

There is a problem in that it takes time to precharge each drain of Mp2 to the power supply potential Vcc, and this precharging time slows down the response of the tristate control. That is, since the entire operating current of the level conversion circuit 1.2 is switch-controlled by the tri-state control circuit 5, the switch control load is heavy, which causes a delay in switching the output state.

An object of the present invention is to provide a technique for reducing input signal transmission speed and response delay of tri-state control as much as possible in a tri-state output buffer circuit having a level conversion function.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

That is, a switch element that is controlled on/off by a tristate control signal is inserted in series between the level conversion circuit and the output circuit section.

[Operation] According to the above-mentioned means, it is possible to reduce the delay elements interposed in series in the transmission path of the logic signal, and to keep the MOS transistor in the level conversion circuit always in an active state precharged to the power supply potential. You will be able to do this.

This achieves the purpose of minimizing input signal transmission delay and tristate control response delay in a tristate output buffer circuit having a level conversion function.

[Examples] Hereinafter, preferred embodiments of the present invention will be described based on the drawings.

In each figure, the same reference numerals indicate the same or corresponding parts.

FIG. 1 shows a first embodiment of an output buffer circuit according to the invention.

The output buffer circuit shown in the figure is a BiCMO3 type high-speed S
It is constructed with the intention of being used as a readout section for storing and reading data in a RAM, and its main parts include first and second level conversion circuits 1, which convert the levels of logic input signals +Lin and -Lin; 2, a complementary output circuit section 3 driven by the outputs 11.21 of the first and second level conversion circuits 1.2, and an output 31 of the output circuit section 3 between H (high level) and L. It is constituted by a tri-state control circuit 5 that switches to a binary output state (low level) or a high impedance state.

The level conversion circuits 1 and 2 are connected to the power supply potential VCC and have mutually complementary logic input signal terminals Lin, -.
The first and second p-channel MOS transistors Mpl, Mp2 are on/off controlled by Lin, and the source current Im of the second M○S transistor Mp2 is controlled by the source current Imi of the first MOS transistor Mpl.
A level-converted output is taken out from the source side of the second MOS transistor Mp2 and given to the output circuit section 3 as a drive signal.

The output circuit section 3 has a bipolar transistor Q1 for pull-up drive, a bipolar transistor Q2 for level shift, and an n-channel MoS transistor Mnl for pull-down drive connected in series between a power supply potential Vcc and a reference potential. Ql-02
An output 31 is derived from an intermediate connection point between and Mnl, a so-called node. Ql and Mnl are controlled on/off in a complementary manner by the outputs 11 and 21 of the level conversion circuits 1 and 2, so that a logic signal Lout of a predetermined level is outputted to the output 31. .

The tri-state control circuit 5 is constituted by a p-channel MOS transistor Mp3.

This p-channel MOS transistor Mp3 is inserted in series between the source side of the second p-channel MOS transistor Mp2 of the level conversion circuits 1 and 2 and the output elements of the output circuit section 3, that is, Ql and Mnl. It operates as a switching element whose on/off is controlled by the state control signal Cin.

Next, the operation will be explained.

In FIG. 1, first, the tristate control signal Cin
When is L, p-channel MOS transistor Mp3 of tri-state control circuit 5 is controlled to be in the on state. In this state, the output 11.21 of the level conversion circuit 1.2 is connected to the pull-up driving bipolar transistor Q1 and the pull-down driving MOS transistor Mnl of the output circuit section 3.
is input as a drive signal. As a result, Ql and Mnl of the output circuit section 3 are controlled to be on/off in a complementary manner. Therefore, the output 31 at this time is the input signal +Lin,
A binary output state is achieved in which an H or L logic signal Lout is output depending on -Lin.

On the other hand, when the tri-state control signal Cin is H, the p-channel MOS transistor Mp3 of the tri-state control circuit 5 is controlled to be off.

Due to this off state of Mp3, the pull-up driving bipolar transistor Q1 and the pull-down driving MOS transistor Mnl of the output circuit section 3 are separated from the second MOS transistor Mp2 of the level conversion circuit 1.2, so that both of them are turned off. become a state. Therefore, the output 31 at this time is the input signal +Lin, -
Regardless of the state of Lin, it is in a high impedance state separated from both the power supply potential Vce side and the reference potential side.

As described above, a tristate operation is performed in which the output 31 takes either the H, L, or high impedance state.

At this time, in the level conversion circuit output buffer circuit described above, in the binary output state, the tristate control circuit 5
A MOS transistor Mp3 is interposed in series in the signal transmission path. However, the form of this intervention is only a passive intervention of the on-resistance between the drain and source of the MO3h run transistor, and no transmission delay occurs due to an active circuit such as a logic gate. That is, the MOS transistor MP3 of the tri-state control circuit 5 is connected to the level conversion circuit 1.
2 and the output circuit section 3, it is not interposed as an active circuit or an amplifier circuit with a relatively large transmission delay, but as a mere transmission path.

Thereby, the signal transmission delay caused by the tri-state control circuit 5 can be kept very small.

In addition, the first and second MOs in the level conversion circuits 1 and 2
The S transistors Mpl and Mp2 are always connected to the power supply potential Vcc and are precharged, regardless of the on/off state of the MOS transistor Mp3 of the tristate control circuit 5. Therefore, when switching from the high impedance state to the binary output state, the MOS transistors Mpl and Mp2 in the level conversion circuits 1 and 2
There is no need to wait for the voltage to be precharged to the power supply potential VCC. Thereby, the response delay of tri-state control can also be significantly reduced.

FIG. 2 shows a second embodiment of the output buffer circuit according to the invention.

Focusing on the differences from the first embodiment described above, in the output buffer circuit of this second embodiment, M is controlled on/off by the tri-state control signal Cin.
Two OS transistors Mp3 are provided, one of which is a level conversion circuit l.

The second MOS transistor Mp2 is inserted in series on the source side of the second MOS transistor Mp2, and the other one is connected to the level conversion circuit 1,
The second MOS transistor Mp1 is inserted in parallel between the drain and source of the first MOS transistor Mp1.

In this second embodiment, the first MOS transistor Mp
Even when l is in an OFF-controlled input state, current for pulling down the outputs 11 and 21 of the level conversion circuits 1 and 2 is caused to flow through the current mirror 4. In other words, even when Cin switches from L to H when +Lin is H and Mpl is off, Mp3 causes current to flow through the current mirror 4 instead of Mpl, causing the level conversion output 11.21 to go to L. to drive the pull down. This results in
The operation of switching the output 31 from the binary output state to the high impedance state can be reliably accelerated.

FIG. 3 shows the third utility model registration application instruction for the output buffer circuit according to the present invention.

In this third embodiment, an n-channel MOS transistor Mn2. 'Mn3 is inserted in parallel with the charge extraction circuit 6, and the MOS transistors Mn2. MN3 is controlled on/off by a tristate control signal Cin.

As a result, as in the case of the second embodiment, the input signal +
Regardless of the states of Lin and -Lin, it is possible to reliably speed up the output state switching operation by the tristate control signal Cin.

FIG. 4 shows a fourth embodiment of the output buffer circuit according to the invention.

In this fourth embodiment, a plurality of MOS transistors Mp forming switch elements of a tri-state control circuit 53.
By connecting Mp3 in series in multiple stages, the tristate control circuit 5 is provided with an AND function.

Although not shown, Mp3. ..., Mp3 can be connected in parallel to provide an OR function.

FIG. 5 shows another embodiment of the switch element constituting the tri-state control circuit 5. In FIG.

As shown in the figure, the switch element of the level conversion circuit control circuit may be a combination of a p-channel MOS transistor Mp3 and an n-channel MOS transistor Mn4 in parallel. In this case, n-channel MoS
A tristate control signal (-Cin) whose phase is inverted by an inverter Ivl is applied to the transistor Mn4.

FIG. 6 shows a first configuration example of a current mirror used in the level conversion circuits 1 and 2.

As shown in the figure, the current mirror can be configured by two n-channel MOS transistors Mn31 and Mn32.

FIG. 7 shows a second configuration example of the current mirror.

The current mirror shown in the figure includes n-channel N10S transistors Mn31. Mn32 and p channel MOS
It is composed of a transistor Mp31, an npn bipolar transistor Q31, and an inverter Iv2, and the current of the current mirror 4 can be controlled by a reference potential VC5.

FIG. 8 and FIG. 9 each show a configuration example of the charge extraction circuit 6.

The charge extraction circuit 6 shown in FIG. 8 includes an n-channel M
It is composed of an OS transistor Mn41 and a bipolar transistor Q41 for level adjustment. Also,
The charge extraction circuit 6 shown in FIG. 9 includes an n-channel MOS transistor Mn41 and a p-channel MOS transistor M.
It is composed of p41 and npn buffer transistors Q41, and performs charge extraction at high speed by a kind of positive feedback latch.

FIG. 10 shows the configuration of an SRAM using the above-mentioned tri-state output buffer circuit in the data output part, in which 101 is an address buffer that receives address signal A1n, 102 is a decoder that creates a storage selection signal,
103 is a memory cell array, 104 is input data D
105 is a control logic that controls the data read/write operation by externally applied control signals O8 and WE; 106 is a sense control section that writes data in and reads output data Dout;
Amplifier 107 is a tri-state output buffer circuit that outputs the data read by sense amplifier 106 to an external bus.

As described above, the tri-state output buffer circuit 107 is configured by the level conversion circuit 1.2 and the output circuit section 3, and receives data input via the buffer 108.
Tri-state control is performed by enable signal DE (corresponding to Cin).

Here, if tristate output buffer circuit 107 is configured as in the above-described embodiment, it becomes possible to speed up the read access of stored data and the response to data enable signal DE. for example,
In the case of a semiconductor integrated circuit device using process technology using the 1.0 μm rule, the data output enable access time is 5.
It becomes possible to make it ~6 nS or less.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor.

For example, the level conversion circuits 1 and 2 may be configured using bipolar transistors.

The above explanation will mainly focus on the BiCMO3 type SR, which is the field of application that was the background of the invention made by the present inventor.
Although the case where the present invention is applied to AM has been described, the present invention is not limited thereto, and can also be applied to, for example, an output buffer circuit of a communication driver.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

That is, in a tri-state output buffer circuit having a level conversion function, an effect can be obtained in that the transmission delay of an input signal and the response delay of tri-state control can be made as small as possible.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a first embodiment of an output buffer circuit according to the present invention, FIG. 2 is a diagram showing a second embodiment of an output buffer circuit according to the present invention, and FIG. 3 is a diagram showing an output buffer circuit according to the present invention. FIG. 4 is a diagram showing a fourth embodiment of the output buffer circuit according to the present invention. FIG. 5 is a diagram showing another embodiment of the switch element constituting the tri-state control circuit. , Figure 6 is a diagram showing a first configuration example of a current mirror used in a level conversion circuit, Figure 7 is a diagram showing a second configuration example of a current mirror, and Figures 8 and 9 are respectively for charge extraction. FIG. 10 is a block diagram showing an example of the configuration of an SRAM using the tri-state output buffer circuit of the present invention in the data output portion, and FIGS. 11 and 12 are diagrams showing another example of the configuration of the circuit. FIG. 2 is a diagram showing the configuration of an output buffer circuit studied in the following. +L i n, -L i n=-・Logic input signal, l
, 2... Level conversion circuit, 11.21... Output of level conversion circuit, 3... Output circuit section, 31...
...Output, 4...Current mirror, Mpl...
First MOS transistor, Mp2...second MO
S transistor, 5... Tri-state control circuit. cc CC in Figure Figure Figure Figure Figure Figure Figure

Claims (1)

[Claims] 1. An output circuit section configured by a first output element that performs pull-up drive and a second output element that performs pull-down drive, and complementary drive of the first and second output elements. first and second level conversion circuits, and first and second level conversion circuits inserted in series between the first level conversion circuit and the first output element and between the second level conversion circuit and the second output element, respectively. an output buffer circuit comprising: a second switch element; the output circuit section is tri-stated by controlling on/off of the switch element; 2. The first and second level conversion circuits each include first and second p-channel MOS transistors that are alternately controlled on/off by mutually complementary logic input signals, and the source of the first p-channel MOS transistor. a current mirror that controls the source current of the second p-channel MOS transistor by a current;
A patent claim characterized in that a level-converted output taken out from the source side of an OS transistor is given as a drive signal to an output element of an output circuit section through a switching element that is controlled on/off by a tri-state control signal in series. The output buffer circuit according to item 1.