JPH05100896A - Debugging support mechanism - Google Patents

Abstract

PURPOSE:To efficiently measure execution time for calling procedure being the neck point of a program by controlling the propriety of exception generation by means of the depth of procedure calling. CONSTITUTION:A procedure counter 21 measures the depth of procedure calling and transmits the measured result to a trace exception detecting circuit 24 with a zero detecting equipment 22. A trace exception generation condition designating register 23 designates condition for generating a trace exception to the detecting circuit 24. Then, the detecting circuit 24 decides the propriety of trace exception generation by the depth of calling measured by the counter 21 at the time of procedure calling or coming back instruction execution. That is, the exception is generated from the trace exception detecting circuit 24 so as to measure called times at the time of procedure calling instruction execution in order to detect procedure calling(sub-routine) which is most frequently called in some program, for example.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a central processing unit (CP
U) relates to a debug support mechanism that supports the detection of errors in the program executed and the correction of those errors.

[0002]

2. Description of the Related Art Conventionally, as a technique in such a field,
For example, some documents were described in the following documents. IPSJ 33rd National Convention Collection (1986) Kawai et al. "SI
MPOS Programming Environment-Call Counter "
P. 417-418 As described in the above document, in a program being debugged, some procedure calls are frequently called, which is often a bottleneck for performance improvement. Therefore, if it is possible to measure which procedure is called and how often during the execution of the program, it can be useful for tuning (accelerating) the program. Therefore, in the technique of the above document, the call frequency of the procedure is measured by providing a flag for a call counter in the intermediate representation of the program.

[0003]

However, in the conventional debug support mechanism, the call counter for the procedure call is realized by software, and in order to measure the number of calls, a dedicated utility routine (for operation support) is used. Routine). Therefore, the following problems occur.

(A) Since the code for operating the call counter is increased and the procedure is executed every time the procedure is called, the overhead (required operating time) is large.

(B) Since it cannot be applied to low-level debugging such as machine language, its application range is limited. Therefore, it is difficult to efficiently measure the execution time of the procedure call.

The present invention provides a debugging support mechanism which solves the problem of the conventional technique that it is difficult to efficiently measure the execution time of a procedure call.

[0007]

SUMMARY OF THE INVENTION The present invention provides a procedure nest counter for measuring the depth of a procedure call and a trace exception in a debug support mechanism for supporting the detection of an error in a program executed by a CPU and the correction of the error. Whether to generate a trace exception is determined based on the depth of the call when a procedure call or return instruction is executed, based on the output of the trace exception occurrence condition specifying means for specifying the condition for generating Trace exception detection means.

[0008]

According to the present invention, since the debug support mechanism is configured as described above, in order to measure the number of executions of the procedure call instruction and the execution time of the called procedure, the procedure nest counter is set The depth is measured and the measurement result is sent to the trace exception detecting means. Furthermore,
The trace exception generation condition specifying means specifies a condition for generating a trace exception to the trace exception detecting means.
Then, the trace exception detection means determines whether or not the trace exception is generated depending on the depth of the call when executing the procedure call or the return instruction. This allows efficient measurement of procedure call execution time. Therefore, the above problem can be solved.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram of the essential parts of a debug support mechanism showing an embodiment of the present invention. This debug support mechanism supports detection of an error in a program executed by the CPU 1 and correction of the error, and the instruction decoding circuit 1
0 and an exception detection circuit 20.

The instruction decoding circuit 10 decodes the program executed by the CPU 1 and outputs the decoding result to the exception detection circuit 20.
Etc., which is a circuit for giving an instruction holding register (CODEREG) 11 for holding an instruction being executed, and the contents of the instruction holding register 11 to decode the control signal INST _- BSR,
An instruction decoder 12 for supplying INST _- BSRCC, INST _- RET to the exception detection circuit 20.

The exception detection circuit 20 is a circuit that determines whether or not a trace exception can be generated based on the output of the instruction decoder 12 or the like when executing a procedure call or a return instruction, depending on the depth of the call. The exception detection circuit 20 is provided with a 32-bit procedure nest counter (SRNC) 21 capable of incrementing / decrementing for measuring the depth of a procedure call, and a zero detector 22 is provided on the output side thereof.
Are connected. The zero detector 22 detects 0 of the procedure nest counter 21 and outputs a signal SRNCZ corresponding to the zero detection.
This is a circuit that outputs ERO (= 1).

The exception detection circuit 20 is also provided with trace exception generation condition designating means for designating a condition for generating a trace exception, for example, a 32-bit trace exception generation condition designating register (TECR) 23. A trace exception detection circuit 24, which is a trace exception detection means, is connected to the output sides of the zero detector 22 and the trace exception generation condition designation register 23. The trace exception detection circuit 24 outputs the output signal SRNCZERO of the zero detector 22, the output signal of the trace exception generation condition designating register 23, and the output control signals INST _- BSR, INST of the instruction decoder 12.
_- BSRCC, INST _- RET, based on the result determined condition code CC of the operational, to determine whether or not to generate the trace exception, a circuit for outputting a signal ERCEXP accordingly.

Next, the operation of the debug support mechanism of FIG.
This will be described with reference to FIGS. 2 and 3. FIG. 2 shows the CPU 1.
It is a figure which shows the list of the procedure call and the return instruction which are defined by. FIG. 3 is a diagram showing a logical state of the trace exception detection circuit 24.

This debug support mechanism operates to support debugging of a program executed by the CPU 1. Here, the procedure call and return instructions defined by the CPU 1 have the contents shown in FIGS. 2 (1) to 2 (3).

That is, FIG. 2A shows an instruction BSR that executes a procedure call unconditionally, and FIG. 2B shows an instruction BSRCC that executes a procedure call when a condition is satisfied.
And (3) of the same figure is an instruction RET for returning from the called procedure to the called place.

Such an instruction is held in the instruction holding register 11 in the instruction decoding circuit 10, the content of the register 11 is decoded by the instruction decoder 12, and the instruction decoder 12 causes the next three control signals INST. _- BSR, INST _- BS
Trace exception detection circuit 24 for RCC, INST _- RET
Output to. (I) When the instruction is an unconditional procedure call instruction, the control signal INST _- BSR is set to 1. (Ii) if the instruction is a conditional procedure call instruction,
The control signal INST _- BSRCC is set to 1. (iii) If the instruction is a procedure return instruction, the control signal IN
ST _- RET is set to 1.

In the exception detection circuit 20, the procedure nest counter 21 and the trace exception occurrence condition designation register 23 are special registers, of which the procedure nest counter 21 executes the instruction BSRCC, and when the condition is true, Alternatively, it is incremented (+1 increment) when the instruction BSR is executed. When the instruction RET is executed, it is decremented (decremented by -1). The 0 state of the procedure nest counter 21 is detected by the zero detector 22, and the detection signal SRNCZERO (= 1) is applied to the trace exception detection circuit 24.

On the other hand, the trace exception occurrence condition designation register 23 is a 32-bit register, and each bit thereof is assigned as shown in (a) to (e) below. In addition,
Bits 5 to 31 of this register 23 are unused.

(A) Bit 0 1; An exception is generated when the unconditional procedure call instruction BSR is executed. 0: No exception is generated even if the unconditional procedure call instruction BSR is executed. (B) bit 1 1; executes the conditional procedure call instruction BSRCC,
And when the condition is true, raise an exception. 0: The conditional procedure call instruction BSRCC is executed,
And even if the condition is true, it does not raise an exception.

(C) Bit 21: The conditional procedure call instruction BSRCC is executed,
And an exception is raised when the condition is false. 0: The conditional procedure call instruction BSRCC is executed,
And even if the condition is false, it does not raise an exception.

(D) Bit 31: An exception is generated when the procedure return instruction RET is executed. 0: No exception occurs even if the procedure return instruction RET is executed. The bits shown below are additional conditions for bits 0 to 3.

(E) Bit 41: An exception is generated when the value of the procedure nest counter becomes 0. 0: An exception is not generated regardless of the value of the procedure nest counter. For example, if bit 4 and bit 3 are set,
The exception generation conditions are "execute the procedure return instruction" and "the value of the procedure nest counter is 0".

The output of register 23 is applied to trace exception detection circuit 24. Trace exception detection circuit 24
Determines whether to generate an exception when TERC <4> is 1 or 0 according to the logic diagram as shown in FIG. 3, and when the exception is generated, sets the output signal ERCEXP to 1
To

As described above, by utilizing the measuring mechanism of this embodiment, it becomes possible to efficiently detect the neck point of the program. For example, in order to detect the procedure call (subroutine) that is most frequently called in a certain program, an exception is generated from the trace exception detection circuit 24 when the procedure call instruction is executed, and the number of times of calling is measured. ..

When the procedure execution time is measured, the subroutine nest counter can be used efficiently. When a procedure is called and a trace exception occurs, the subroutine nest counter is set to 1. Trace exception generation condition specification register 2
Bits 3 and 4 of 3 are set to 1, and other bits are set to 0. As a result, the conditions for the trace exception to be generated from the trace exception detection circuit 24 are "when the procedure return instruction is executed" and "when the value of the procedure nest counter 21 becomes 0". Therefore, the trace exception detection circuit 24 does not generate a trace exception until the instruction returning to the routine that called this procedure is executed. Therefore, the execution time of the procedure call can be efficiently measured without any overhead.

The present invention is not limited to the above embodiment,
Various modifications are possible. For example, in FIG. 1, the number of bits of the procedure nest counter 21 and the trace exception occurrence condition designation register 23 may be set to an arbitrary number of bits, or the register 23 may be configured by the trace exception occurrence condition designation means of another circuit. In addition, the trace exception detection circuit 24
May be composed of other trace exception detecting means such as program control of the CPU 1 instead of being composed of an individual circuit. Further, in order to improve the accuracy of the measurement mechanism, various circuits such as other registers and flags can be added to the debug support mechanism of FIG.

[0027]

As described above in detail, according to the present invention, since the procedure nest counter, the trace exception occurrence condition designating means and the trace exception detecting means are provided, whether or not an exception can be generated depending on the depth of the procedure call. Can control
As a result, the number of executions of the procedure call instruction and the execution time of the called procedure can be measured. Therefore, it is possible to efficiently measure the execution time of the procedure call, which is the neck point of the program.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a main part of a debug support mechanism showing an embodiment of the present invention.

FIG. 2 is a diagram showing a list of procedure call and return instructions defined by a CPU.

FIG. 3 is a diagram showing a logical state of a trace exception detection circuit.

[Explanation of symbols]

 1 CPU 10 Instruction Decoding Circuit 20 Exception Detection Circuit 21 Procedure Nested Cowcata 23 Trace Exception Generation Condition Designation Register 24 Trace Exception Detection Circuit

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Kenji Kato 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd.

Claims (1)

[Claims] 1. A debug support mechanism for supporting detection of an error in a program executed by a central processing unit and correction of the error, by specifying a procedure nest counter for measuring the depth of a procedure call and a condition for generating a trace exception. Trace exception occurrence condition designating means and trace exception detection means for deciding whether or not to generate a trace exception according to the depth of the call when executing a procedure call or a return instruction based on the outputs of the procedure nest counter and the trace exception occurrence condition designating means. , A debugging support mechanism characterized by being provided.