JPH051225U - Lead frame for semiconductor device - Google Patents

Abstract

(57) [Summary] [Structure] A hole 3 is formed in an island 2 to be die-bonded. [Effect] The sealing resin 7 is placed in the hole 3 formed in the island 2.
Can be mitigated the stress generated by the difference in the coefficient of thermal expansion between the chip 6 and the island 2, and the crack of the chip 6 can be prevented. For this reason, it is not necessary to thicken the silver plating layer 4 formed as a cushioning material on the island 2, so that the manufacturing cost can be reduced.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a lead frame of a semiconductor device, and more particularly to a lead frame of a semiconductor device having an island for die bonding a semiconductor chip.

[0002]

[Prior Art]

 In a conventional lead frame of a semiconductor device, as shown in FIG. 3, an island 12 for die-bonding a semiconductor chip (hereinafter referred to as a chip) 6 has a flat plate shape.

[0003]

[Problems to be solved by the device]

 In a conventional lead frame for a semiconductor device, a chip crack caused by a difference in coefficient of thermal expansion between a chip 6 and an island 12 for die-bonding the chip 6 is a problem during die bonding using a solder 5. It was

As a countermeasure against chip cracks, a method of forming a silver plating layer 4 on the island 12 and using it as a cushioning material between the chip 6 and the island 12 is used. Since the occurrence rate of cracks increases, the thickness of the silver plating layer 4 also needs to be increased in proportion to the size of the chip 6, resulting in a problem of increased manufacturing cost.

An object of the present invention is to provide a lead frame of a semiconductor device which can obtain an inexpensive semiconductor device without chip cracks.

[0006]

[Means for Solving the Problems]

 The present invention relates to a lead frame of a semiconductor device having an island on which a semiconductor chip is mounted, a silver plating layer covering the island, and a lead connected to an electrode of the semiconductor chip and led out of a sealing resin. , Make a hole in the island.

[0007]

【Example】

 Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a plan view of an essential part of an embodiment of the present invention, and second is a sectional view in which a chip is mounted on the island of FIG. 1 and sealed with a sealing resin.

As shown in FIGS. 1 and 2, a hole 3 is formed in advance in an eyeland 2 on which a chip 6 is mounted by die bonding. The shape of the hole 3 is such that the opening of the chip mounting surface of the island 2 is made small and the opening of the back surface is made large in a mortar shape so that the sealing resin 7 can easily enter from the back surface of the island 2. Then, the stress generated by the difference in the coefficient of thermal expansion between the chip 6 and the island 2 is relaxed by the sealing resin 7 filled in the hole 3 to prevent the chip 6 from cracking.

Therefore, the silver plating layer 4 formed as a cushioning material on the island 2 does not need to be thickened in proportion to the size of the chip 6, so that the manufacturing cost can be reduced.

[0011]

[Effect of the device]

 As described above, according to the present invention, in the lead frame of the semiconductor device, a hole is formed in the island for die-bonding the chip, and the sealing resin penetrates into the hole. It has the effect of relaxing the stress generated by the difference in expansion coefficient and preventing chip cracks.

Further, it is not necessary to increase the thickness of the silver plating layer in proportion to the size of the chip, and the manufacturing cost can be reduced.

[Brief description of drawings]

FIG. 1 is a plan view of an essential part of an embodiment of the present invention.

FIG. 2 is a cross-sectional view of a chip mounted on the island of FIG. 1 and sealed with a sealing resin.

FIG. 3 is a sectional view showing a chip mounted on an example of a lead frame of a conventional semiconductor device.

[Explanation of symbols]

 1 Lead 2, 12 Island 3 Hole 4 Silver plating layer 5 Solder 6 Chip 7 Sealing resin

Claims (1)

[Claims for utility model registration] [Claim 1] An island on which a semiconductor chip is mounted,
A hole is provided in the island in a lead frame of a semiconductor device having a silver plating layer covering the island and a lead connected to an electrode of the semiconductor chip and led out of a sealing resin. Lead frame for semiconductor devices.