JPH0512878A - Semiconductor memory circuit - Google Patents

Abstract

(57) [Summary] [Object] A semiconductor memory circuit according to the present invention shortens the charging / discharging time of a data line at the time of data reading. [Structure] A semiconductor memory circuit according to the present invention has, as a basic component, a flip-flop circuit formed by using two inverter circuits each including a transistor and a load element. Then, a read-only data line is provided. A control electrode is connected to the output end of the inverter circuit, and an electrode in which the state of the inverter circuit appears based on the signal of the output end is connected to the read-only data line. A control electrode is connected to a given read word line, and a drive transistor for driving the output transistor is provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory circuit which can be operated at high speed and is used in computers and various communication devices.

[0002]

2. Description of the Related Art As shown in FIG. 2, a conventional semiconductor memory circuit has a FET2 in which a gate and a source are short-circuited.
Two inverter circuits are connected in which 1 and 23 are loads and FETs 22 and 24 whose drains are connected to the loads are input transistors are connected to form a flip-flop circuit. The FETs 25 and 26 are transfer gates, and the data lines Y, Y and the output terminals (points) of each of the above-mentioned inverter circuits according to the signal (voltage) given to the word line X.
Contact A and B. The voltage V _DD is applied to the drains of the FETs 21 and 23, and the voltage V _SS is applied to the sources of the FETs 22 and 24. In such a semiconductor memory circuit, in order to read data, a high-level voltage is applied to the word line X to bring the FETs 25 and 26, which are transistor gates into a conductive state, and the potential at the point A to the data line Y The potential of the point is transmitted to the data line Y.
Further, in order to write data, a high level voltage is applied to the word line X again to open the transfer gate, and signals corresponding to the desired state of writing are applied to the data lines Y and Y.

[0003]

[SUMMARY OF THE INVENTION Incidentally, in the conventional memory, the data line Y, at least several tens of memory cells are connected to the Y, the data line Y, the length of Y is a few mm
Can extend to Therefore, when reading the memory,
The data lines Y, Y having such a large wiring capacity must be charged / discharged by the charges of the small memory cells, and in order to perform high-speed memory access, the charging / charging time for the data lines Y, Y is to be increased. The issue is to shorten

Therefore, a method of limiting the signal amplitude and a method of precharging by connecting various additional circuits to the data line have been tried. However,
When the signal amplitude of the data line is limited, the operation margin is narrowed, and especially in the case of GaAs-MESFET or the like in which the unevenness of the device characteristics has not been sufficiently solved, the yield decreases, and it is difficult to achieve both high-speed operation and high yield. there were. On the other hand, precharging requires a precharge time, and there is a limit to the speedup.

Therefore, it is an object of the present invention to provide a semiconductor memory circuit which can operate at high speed by shortening the data line charging / discharging time at the time of data reading without lowering the yield.

[0006]

SUMMARY OF THE INVENTION The present invention is a semiconductor memory circuit having a flip-flop circuit formed by using two inverter circuits each including a transistor and a load element. The data line, the read data line where the read data appears, and the output end of the inverter circuit are connected, and the electrode where the signal corresponding to the state of the inverter circuit appears based on the signal of the output end is the read data line. It is characterized in that it is provided with a connected output transistor, a read word line to which a signal for controlling data read is given, and a drive transistor for driving the output transistor based on the signal of the read word line.

[0007]

Since the semiconductor memory circuit according to the present invention is configured as described above, the drive transistor is controlled via the read word line, and as a result, the output transistor is controlled by the drive transistor and the read data is read. The line is driven and a signal corresponding to the state of the inverter circuit appears on the read data line.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor memory circuit according to an embodiment of the present invention will be described below with reference to FIG. 1 of the accompanying drawings.

Even in this semiconductor memory circuit, the FETs 21 and 23 having the gate and the source short-circuited are used as loads, and the drains are connected to the FETs 22 and 24.
A basic configuration element is a flip-flop circuit in which two inverter circuits each having an input transistor are connected.
The FETs 25 and 26 are transfer gates, and connect the write data lines Y _W and Y _W and the output terminals (points) A and B of the above inverter circuits in accordance with the voltage given to the write word line X _W. Let me know. The voltage V _DD is applied to the drains of the FETs 21 and 23, and the voltage V _SS is applied to the sources of the FETs 22 and 24.

In this embodiment, the output transistor F is used.
ET1 and ET2 are provided. The FETs 1 and 2 have their gates connected to the output terminals (points) B and A of each inverter circuit, respectively, and their drains connected to the read (dedicated) data lines Y _R and Y _R , respectively. Further, a read-only read word line X _R is provided, and the read word line X _R is a driving transistor FE.
It is connected to the gate of T3. The drain of the FET 3 is connected to the sources of the FETs 1 and 2, and the source is supplied with the voltage V _SS .

In such a semiconductor memory circuit, in order to write data, a high level voltage is applied to the write word line X _W to form a transfer gate F.
The ETs 25 and 26 are made conductive, and signals corresponding to the state to be written are applied to the write data lines Y _W and Y _W.
On the other hand, in order to read data, a high level signal is given to the read word line X _R. This allows
The FET3, which is a drive transistor, becomes conductive, and the FETs 1, 2 that are output transistors are transitioned to an operable state. Here, assuming that the potential of the output terminal B of the inverter circuit having the load of the FET 21 is high level and the potential of the output terminal A of the inverter circuit having the FET 23 of the load is low level, the FET 1 is in the conductive state and the FET 2 is in the cut-off state. Becomes As a result, it appears low level voltage to the read data line Y _R, the read data lines Y _R
A high level voltage appears at.

As described above, in this embodiment, the FETs 1 and 2 which are output transistors are driven by the FET 3 which is a drive transistor at the time of reading the data, and the FETs 1 and 2 are driven.
Is enabled. As a result, the FETs 1 and 2 are brought into a state of driving the read data lines Y _R and Y _R , so charging and discharging are performed at a higher speed than a conventional circuit that drives the data lines with a small amount of charges in the memory, and a high speed operation is performed. Is secured.

In the embodiment, since the number of transistors and the number of signal lines increase, the area of the unit memory cell increases, but high speed operation is required even with a relatively small memory capacity. It is optimum in a field, for example, a register file used inside the CPU.

[0014]

As described above, according to the present invention,
At the time of reading data, the read-only data line is driven by the output transistor driven by the drive transistor, so that the charge and discharge of the data line can be performed with a charge having a much larger capacity than the charge in the conventional memory cell. It is made possible and enables high speed operation.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a semiconductor memory circuit according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of a conventional semiconductor memory circuit.

[Explanation of symbols]

1, 2 ... FET (output transistor) 3 ... FET (driving transistor) 21, 23 ... FET (load transistor) 22, 24 ... FET (input transistor) 25, 26 ... FET (transfer gate) X _R ... Read word line X _W ... write word line Y _R , Y _R ... read data line Y _W , Y _W write data line

Claims (1)

Claim: What is claimed is: 1. A semiconductor memory circuit having a flip-flop circuit formed by using two inverter circuits each including a transistor and a load element, and a write data line in which write data appears, A read data line in which the read data appears and an output terminal of the inverter circuit are connected, and an electrode in which a signal corresponding to the state of the inverter circuit based on the signal of the output terminal appears is connected to the read data line. A semiconductor memory circuit comprising: an output transistor, a read word line to which a signal for controlling data read is given, and a drive transistor which drives the output transistor based on a signal of the read word line.