JPH05129944A - Pll circuit - Google Patents

Abstract

(57) [Summary] (Modified) [Purpose] To realize a PLL circuit that does not cause settling when the frequency is forcibly set using an auxiliary circuit. [Structure] A phase comparator circuit 1, a switch 2 for controlling whether or not to connect to a circuit in a subsequent stage by using a signal input from a frequency detection means 8, and output as an output voltage level from the phase comparator circuit 1 and the like. Phase voltage converter 3, VCO 4 which outputs a signal having a frequency proportional to this voltage, and VCO 4
Frequency detection means 8 for outputting a signal to the switch 2 and the following signal delay circuit 7 when the set frequency matches the signal from the frequency detection means 8, and the signal from the frequency detection means 8 is input and based on the signal. A signal delay circuit 7 for generating the signal after delaying for a set time, and the signal delay circuit 7
A PLL circuit including a voltage adding means 6 for outputting a voltage level to be added to the phase voltage converter 3 based on the signal from.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked loop circuit (hereinafter referred to as a PLL circuit), and more particularly to a PLL circuit forcibly setting a frequency using an auxiliary circuit.

[0002]

2. Description of the Related Art FIG. 5 is a diagram showing a configuration of a PLL circuit forcibly setting a frequency by using an auxiliary circuit. Reference numeral 1 is a phase comparator, which is a reference signal and a voltage-controlled oscillator (hereinafter referred to as V
(Referred to as CO) 4 and the phase of the signal with the output signal from 4 are adjusted and adjusted. Reference numeral 2 denotes a switch, which is turned on / off by a signal from the frequency detecting means 8. Reference numeral 3 denotes a phase-voltage conversion circuit, which integrates a voltage having a level proportional to the frequency of a signal input from the phase comparator 1 through the switch 2 and a voltage level of the voltage input from the voltage adding means 5. And output.
This is composed of an amplifier, an integrator including a resistor R1 and a capacitor C, and the like. Reference numeral 4 denotes a voltage controlled oscillator, that is, a VCO, which outputs a frequency proportional to the voltage level input from the phase voltage conversion circuit 3. Reference numeral 5 is a low-pass filter (hereinafter referred to as LPF) that blocks high-frequency components of the output signal from the mixer 9 and feeds it back to the phase comparator 1. Reference numeral 6 is a voltage adding means, which comprises a voltage source and a switch for switching the voltage source. This switch is switched by the signal from the frequency detecting means 8. A mixer 9 synthesizes a reference signal and the frequency of the signal from the voltage controlled oscillator. Of these, the voltage addition means 6 and the frequency detection means 8 constitute an auxiliary control circuit.

The operation of the auxiliary control circuit in the thus configured PLL circuit will be described. Originally, the PLL circuit controls to gradually become the target frequency.
For example, if you suddenly change the frequency setting you want to output,
There are times when you want to approach that frequency as quickly as possible. At this time, an auxiliary control circuit is used to add a positive or negative voltage and forcibly bring it closer to the target frequency. V at this time
FIG. 7 shows the time variation of the input voltage Vc of CO4. In this case, the VCO 4 has a proportional relationship between the input voltage and the output frequency. The state 1 in FIG. 7 means that the switch 2 is turned on and the changeover switch (hereinafter referred to as S
(Referred to as W) is connected to (b) shown in FIG.
It refers to what constitutes a loop for operating the LL circuit. State 2 means that the switch 2 is turned off and the voltage adding means 6
SW in FIG. 5 is connected to (C) shown in FIG. 5, and the voltage is added to the phase voltage conversion circuit 3 to force the target frequency (see FIG. 7).
Then it is close to Vc). At this time, as shown in FIG. 7, a voltage drop occurs when the state 2 changes to the state 1. The reason for this will be described below.

FIG. 6 shows the structure of a portion where a voltage drop occurs. In the figure, the same parts as those in FIG.
Vc of the output of the phase voltage conversion circuit 3 in the state 2 is as follows. Since the voltage is applied from the power source in the voltage adding means 6, the current i flows. Therefore, a potential of V _R1 = i × R1 (resistance value) is generated across the resistor R1, and a potential of V _cap = (i × t) / C (capacitance value) across the capacitor C. Since it occurs, Vc = V _R1 + V _cap = i × R1 + (i × t) / C.

Here, the moment when the state 2 (the state in which the target frequency is forcibly approached) is switched to the state 1 (the control state in the normal PLL circuit) will be described. At this time, the output of Vc temporarily decreases as shown in FIG. It should be noted that this decrease in output must be repaired by controlling the PLL circuit, which takes time. The reason why the output of Vc is temporarily reduced will be described below. Again, consider the configuration shown in FIG. The SW in the voltage adding means 6 is connected to (B) shown in FIG. 5 and one side of the resistor R2 is opened, so that the current i flowing in the state 2 stops flowing. At this time, the potential across the capacitor C holds the last V _cap of the state 2 until the current flows again,
Since the current no longer flows through the potential across the resistor R1, V _R1
= 0. Therefore, from state 2 to state 1 by V _R1
The voltage drops at the moment of switching to.

[0006]

Therefore, in the output of the PLL circuit in which the frequency is forcibly set by the auxiliary control circuit, when the state in which the frequency is forcibly set is switched to the normal control state. There is a problem that a stable output cannot be obtained because the frequency changes. An object of the present invention is to solve such a problem and to realize a PLL circuit that can obtain a stable output even when switching states.

[0007]

DISCLOSURE OF THE INVENTION The present invention provides a phase comparison circuit for comparing a reference signal and an input signal phase, and the phase comparison circuit using a signal input from the frequency detection means described below. A switch for controlling whether or not to connect to the circuit of, a phase voltage converter for adding the output from the phase comparison circuit and the output from the voltage adding means described below and outputting as a voltage level, and the phase voltage converter A voltage-controlled oscillator that outputs a signal with a frequency proportional to the input voltage of
A mixer that synthesizes a reference signal and the frequency of the signal from the voltage controlled oscillator, a low-pass filter that blocks high-frequency components of the output signal from the mixer, and a signal from the voltage controlled oscillator are input, and an input signal is input. When the set frequency matches the frequency detection means for outputting a signal to the switch and the following signal delay circuit, and the signal from the frequency detection means is determined from the inside of the circuit of the phase voltage converter depending on the conditions. A signal delay circuit for outputting with or without delay by a constant time, and a voltage adding means for outputting a voltage level to be added to the phase voltage converter based on the signal from the signal delay circuit. PL to
It is an L circuit.

[0008]

When the state changes, the output voltage Vc of the phase voltage conversion circuit 3 as a result of the voltage drop becomes a voltage for the target frequency, so that it is delayed from the moment when the target frequency is detected (time T) Change the state. This state is shown in FIG. This because the state change, voltage Vc (indicates a voltage drop which has been flowing to the resistor, in the prior art are those referred to as V _R1.) VR even changes occur only, it is an object of the frequency Since it is Vc for, it is possible to prevent a frequency change from occurring.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows the basic configuration of the present invention. 1 that are the same as those in FIG. 5 are assigned the same reference numerals. A signal delay circuit 6 delays and outputs a signal from the frequency detecting means 8 when the frequency is forcibly set to a normal control state, and is forcibly changed from the normal control state. When the frequency changes to the set state, the signal from the frequency detecting means 8 is output without delay. Signal delay circuit 6
The voltage addition means 6 outputs the voltage level to be added to the phase voltage converter 3 based on the signal from The addition of the signal delay circuit 6 to the conventional configuration is the PLL circuit shown in FIG.

FIG. 2 shows an embodiment of the present invention. 70 is a decoder. Reference numerals 71, 72, 73 and 74 are one-shot triggers that output an H level by a falling edge operation, and 71 and 73 have a delay time of time T.
Has a delay time of 2T (twice T). 75,7
Reference numerals 6, 77 and 78 are NOR circuits. 79 is AND. SW1, SW2, and SW3 are switches that are turned on / off by a signal from the decoder 70. Switch 2 is realized by a tri-stite buffer. Delay time T at this time
Corresponds to the time when the voltage is additionally accumulated by the amount corresponding to the change in the voltage Vc when the state 2 is changed to the state 1 after the target frequency is detected. In addition, state 3 is
The switch 2 is turned off, the SW in the voltage adding means 6 is connected to (a) shown in FIG. 5, and a positive voltage is added to the phase-voltage conversion circuit 3 to force the target frequency (Vc in FIG. 7). Is approaching. In this case, the voltage is forcibly lowered.

FIG. 3 shows a time chart of the time change of the output when the PLL circuit having the above structure shifts from the state 2 to the state 1. The section in which the frequency Fout is increasing is the state 2, and when it is sharply decreasing, it indicates the moment when the state 2 is changed to the state 1, and when the frequency Fout is a constant state in Fdata, the state 1 is changed. Show. At this time, the frequency F
The frequency detecting means 8 detects that out is equal to Fdata, and outputs the signal to the signal delay circuit 7. Signal delay circuit 7
Then, this signal is delayed by time T and output for changing from state 2 to state 1. For this reason, the output of the frequency Fout becomes extra by VR as described in FIG.
When the state changes from 1 to state, VR decreases, so the frequency Fout
Is constant at Fdata. By the way, as described in the conventional example, in state 2 and state 3, a positive or negative power source is added to forcibly change the voltage. Therefore, state 2 and state 3 are changed to state 1. At this time, since the current i in FIG. 6 becomes 0, a voltage change occurs. Therefore, the voltage also changes when changing from the state 1 to the state 2 and the state 3, but at this time, since it is originally the case where Fdata changes and the voltage Vc is to be greatly changed, the time T in the signal delay circuit 7 is changed. No delay is needed. The embodiment of FIG. 2 corresponds to such a change in state. When the state 2 and the state 3 are changed to the state 1, the signal for switching is delayed by the time T, and the state 1 to the state 2 is changed. When the state changes to state 3, the signal for switching is output without delay.

FIG. 4 shows a change with time in each state of the operation of such a structure. Also, A, B of the time chart,
(A), (b), (c), (d), (e), (f) A'and B'indicate respective points in FIG. Here, the values of A, B and A ′, B ′ and switches or states 1, 2, 3 will be described. In the frequency detecting means 8, the output frequency Fou
The set frequency Fdata is compared with t, and A and B are output as shown in the table below.

[Table 1] In the case of the conventional example, this is a decoder and a direct switch.
By switching to (a), (b), and (c), the switching between the voltage forced addition state and the normal control state is performed. The tristate buffer, which is the switch 2, is turned on when the state 1 is entered. The decoder 70 inputs the signals A ′ and B ′ and determines which of the switches SW1 to SW3 should be turned on. The relationship is shown in the table below.

[Table 2]

From the left end of FIG. 4, state 2 to state 1,
The state changes from state 3 to state 1, state 1 to state 2, and state 1 to state 3. First, state 2 to state 1
The operation when changing to is described. At this time, state 2 is initially
Therefore, Fout <Fdata, and the frequency detection means 8
The output A is L level, and the output B is H level.
At this time, since the voltage Vc is integrated, Fout = Fdat
Since it passes through a and Fout> Fdata, the frequency detecting means 8
The output A is H level, and the output B is L level.
Now, as shown in FIG. 4, B passes when Fout = Fdata is passed. Due to this fall, a pulse having a time width T from the one-shot trigger 73 is output as shown in (b). Further, as shown in (d), the one-shot trigger 74 outputs a pulse having a time width of 2T. At this time, the NOR 76 inputs B and (b) and outputs the inversion (f) of the logical sum. Therefore, the output B'of Noah 78 is B
Falls a time T later than the moment when L becomes L level. At this time, the frequency Fout of the output of VOC4 is Fout =
Even after passing through Fdata, the state 2 remains continuous for the time T, so that Fout> Fdata and A is at H level and B is
Becomes L level. However, since B'is in the falling state 1, the frequency Fout of the output of the VOC 4 becomes Fout.
= Fdata, and A becomes L level. Therefore, at this time, a fall occurs at A, and from this moment (a)
The pulse of time T is output from the one-shot trigger 71 shown in FIG.
A pulse of T is generated. At this time, Noah 75 has A and (a)
Is input and the logical inversion (e) is output. Further Noah 7
7 inputs (e) and (d) and outputs the inversion A'of the logical sum. At this time, since (e) and (d) are in an inverse relationship, A'is held at the L level regardless of the state change, and therefore the output of VCO 4 is Fout <Fdata to Fout =
Although the state of Fswitch is Fdata>Fout> Fdata and is stable at Fout = Fdata, the state of the switch only changes from state 2 to state 1.

The operation when changing from state 3 to state 1 is A
Taking the fact that A is at the H level and B is at the L level in the initial state 3 with reference to the trailing edge of, the operation may be considered in the same manner as the above description of the operation. The same applies to the operation when changing from state 1 to state 2 or from state 1 to state 3. Therefore, when changing from state 2 and state 3 to state 1, the signal for switching is delayed by the time T, and when changing from state 1 to state 2 and state 3, switching is performed without delay. It has been described in detail that the signal for outputting can be output by using the configuration of the embodiment.

The setting of the time T will be described. Here, description will be given using FIG. 6 and other reference numerals used in the description of the conventional example. It suffices to charge the capacitor by the amount of the voltage VR that fluctuates according to the change in the state described in the conventional example.
The voltage charged in this capacitor is represented by V _cap T. Therefore, the voltage appearing across the capacitor at time T can be expressed as: V _R1 = V _cap T = (i × T) / C (capacitance value) Here, since V _R1 = i × R 1 (resistance value), the relationship between the resistance value, the capacitance, and the time is as follows. i × R1 = (i × T) / C Therefore, when the time is represented by a resistance value and a capacitance, the following equation is obtained. Therefore, the time T in the embodiment can be determined by a given constant.

[0016]

【The invention's effect】 [Brief description of drawings]

FIG. 1 is a basic configuration diagram of the present invention.

FIG. 2 is a configuration diagram of an embodiment of the present invention.

FIG. 3 is an explanatory diagram of the operation of the present invention.

FIG. 4 is an explanatory diagram of an internal operation of the present invention.

FIG. 5 is a basic configuration diagram of a conventional example.

FIG. 6 is an explanatory diagram of a conventional example and an improvement point of the present invention.

FIG. 7 is an explanatory diagram of an operation.

FIG. 8 is an explanatory diagram of an operation.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 phase comparator 2 switch 3 phase voltage conversion circuit 4 voltage controlled oscillator 5 LPF 6 voltage addition means 7 signal delay circuit 8 frequency detection means 9 mixer

Claims (1)

[Claims] 1. A phase comparison circuit for comparing a reference signal with an input signal phase, and whether or not the phase comparison circuit is connected to a circuit in a subsequent stage by using a signal input from a frequency detecting means described below. A switch for controlling, a phase voltage converter for adding the output from the phase comparison circuit and the output from the voltage adding means described below and outputting as a voltage level, and of a frequency proportional to the input voltage from the phase voltage converter. A voltage-controlled oscillator that outputs a signal, a mixer that synthesizes a reference signal and the frequency of the signal from the voltage-controlled oscillator, a low-pass filter that blocks high-frequency components of the output signal from the mixer, and the voltage-controlled oscillator Frequency detection means for outputting a signal to the switch and the signal delay circuit described below when the input signal and the set frequency match. A signal delay circuit for outputting the signal from the number detection means with or without delay by a time constant for a time constant determined from the inside of the circuit of the phase voltage converter according to conditions, and based on the signal from the signal delay circuit. , A PLL circuit comprising voltage adding means for outputting a voltage level to be added to the phase voltage converter.