JPH03214925A - Pll synthesizer circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] Regarding a PLL synthesizer circuit that operates to match the output signal frequency with a set frequency, the short-circuit time of the LPF by the switching circuit is automatically adjusted according to the pull-in time of the LPF. In order to shorten the lock-up time, the voltage signal output from the PLL control unit is passed through the LPF based on the frequency and phase difference between the setting signal based on the external setting frequency and the output signal of the voltage controlled oscillator. output to a voltage controlled oscillator to match the output signal frequency of the voltage controlled oscillator with a set frequency, and receive a phase difference signal based on the phase difference between the set signal and the output signal of the voltage controlled oscillator from the PLL control unit. , a PLL synthesizer circuit including a lock detection circuit that outputs an unlock signal when the phase difference is greater than or equal to a predetermined value and outputs a lock signal when the phase difference is less than or equal to the predetermined value, the unlock signal of the lock detection circuit being A switching circuit that closes (turns on) based on the lock signal and opens (turns off) based on the lock signal is connected in parallel with the LPF between the PLL control section and the voltage controlled oscillator.

[Industrial application field]

The present invention relates to a PLL synthesizer circuit that operates so that the output signal frequency always matches the set frequency.

The PLL synthesizer circuit is a negative feedback circuit that operates to match the set frequency and the output signal frequency, but a low-pass filter is interposed in the negative feedback rope to improve the signal purity of the output signal. . Therefore, when switching the set frequency, a lock-up time based on the time constant of the low-pass filter is required until the output signal frequency is fixed to the set frequency.

[Conventional technology]

An example of a conventional PLL synthesizer circuit will be described with reference to FIG.
When the strobe signal STB is input with TB being input and the setting frequency data DA being input, the setting frequency data DA is input to the PLL calculation unit l based on the clock signal CK.
will be written to. Then, the PLL calculation unit l divides the setting frequency data DA based on the reference frequency of the crystal oscillator 2 and outputs the setting signal fr to the phase comparator 3.

Further, an output signal of a brisk rough, which will be described later, is input to the PLL calculation unit 1, and the PLL calculation unit 1 divides the frequency of the output signal of the prescaler 7 and outputs the resultant signal to the phase comparator 3 as a feedback signal fp.

Based on the setting signal fr and the feedback signal fp, the phase comparator 3 generates a pulse signal φr, which corresponds to the frequency and phase difference between both signals.
φp is output to the charge pump 4, and the charge pump 4 outputs, for example, an output signal SGl shown in FIG. 6 to a low-pass filter 5 (hereinafter referred to as LPF) based on the pulse signals φr and φp. This output signal SGI includes a pulse component in a DC component, and the DC component rises and falls with frequency fluctuations of the pulse signals φr and φp.
The pulse component changes based on the phase difference between the pulse signals φr and φp.

The LPF 5 smoothes the output signal SGl of the charge pump 4 and removes the pulse component, and outputs the output signal SG2 to the voltage controlled oscillator 6 (hereinafter referred to as vCO), and the VCO 6 is set to the L level.
An output signal SG3 having a frequency corresponding to the voltage value of the output signal SG2 of the PF5 is output.

Further, the output signal SG3 of the VCO 6 is frequency-divided by the brise scaler 7, and fed back to the PLL calculation section 1, where the PLL
The frequency of the signal is further divided by the calculation section 1 and outputted to the phase comparator 3 as the feedback signal fp.

In such a PLL synthesizer circuit, when the setting frequency data DA is raised by external input, the frequency of the setting signal fr output from the PLL operation unit l is raised in response to the input of the strobe signal STH, and the output signal SGI of the charge pump 4 is increased. As the DC level of the LPF 5 increases, the voltage value of the output signal SG2 of the LPF 5 also increases, and accordingly, the frequency of the output signal SG3 of the VCO 6 also shifts from the previously set frequency to the newly set frequency. Since the output signal S63 of the VCO 6 is fed back to the PLL calculation section 1 via the brise scaler 7, this negative feedback loop operates so that the feedback signal fp matches the new setting signal. Furthermore, when the setting signal fr is lowered, the output signal SG of the charge pump 4
The DC level of I decreases and similarly converges to the new set frequency.

In the PLL synthesizer circuit as described above, the output signal SGI of the charge pump 4 is output to the VCO 6 via the LPF 5, so the DC level of the output signal SGI of the charge pump 4 fluctuates based on changes in the set frequency data DA. There is a lock-up time based on the time constant of the LPF 5 until the frequency of the output signal SG3 of the VCO 6 converges to the new set frequency, and when this PLL synthesizer circuit is used as a tuner, there is a lock-up time between There is a problem that tuning becomes impossible and noise is output.

Therefore, in order to solve this problem, an analog switch 8 as a switching circuit is connected in parallel to the LPF 5 as shown in FIG. 4, and the strobe signal STB is input to the analog switch 8, and the strobe Only when the signal is input, the analog switch 8 is closed to short-circuit the charge pump 4 and the VCO 6. On the other hand, a lock detection circuit 9 is connected to the phase comparator 3, and the phase comparator 3
When the output signal Δf includes a pulse component based on the phase difference between the setting signal fr and the feedback signal fp, the lock detection circuit 9 outputs an unrotter signal, and the frequency and phase of the setting signal FR and the feedback signal fp are changed. Match phase comparator 3
When the output signal Δf does not contain a pulse component, the lock detection circuit 9 outputs a lock signal, and the tuner output is cut based on the output of the unlock signal, thereby suppressing the output of non-tuning noise. It is prevented.

With such a configuration, for example, when the setting frequency data DA is obtained by external input, the frequency frl of the setting signal fr output from the PLL calculation unit l upon input of the strobe signal STB, as shown by the solid line in FIG. is raised to fr2, and the DC level of the output signal SGl of the charge pump 4 rises, so that the voltage value of the output signal SG2 of the LPF 5 also rises. At this time, the analog switch 8 is closed by the input of the strobe signal STB, and the output signal SGI of the charge pump 4 is directly supplied to the VCO 6.
Therefore, before the voltage value of the output signal SG2 of the LPF 5 increases, the frequency of the output signal SG3 of the VCO 6 shifts from the previously output frequency Fl to the newly set frequency F2, and the strobe signal STB After the input is stopped, the output signal SG3 of the VCO 6 is maintained at the frequency F2 based on the output signal SG2 of the LPF 5.

Therefore, the lock-up time is shortened and the output of noise during the lock-up time is also prevented.

[Problem to be solved by the invention]

However, in the above-mentioned PLL synthesizer circuit, for example, when the set frequency data DA is greatly changed, the voltage rise of the output signal SGI of the charge pump 4 increases as shown by the chain line in FIG. S61
Based on this, the pull-in time tl required until the voltage value of the output signal SG2 of the LPF 5 finishes rising becomes longer.

Then, the output signal SGI of the charge pump 4 is directly output to the VCO 6 via the analog switch 8.
When the output of the strobe signal STB is stopped after the output signal SG3 of 6 is raised to the frequency F2, the VCO
6 receives an output signal SG2 from the LPF 5, which has a voltage lower than the voltage value that had been input from the charge pump 4 up to that point.

Therefore, as shown by the chain line in the figure, the frequency of the output signal SG3 of the VCO 6 rises for a while and then falls, and then rises along with the output signal SG2 of the LPF 5.
Lockup time becomes longer.

Therefore, in order to solve the above problems, LPF
There is a problem in that it is necessary to adjust the pulse width of the strobe signal STB in accordance with the pull-in time of 5.

An object of the present invention is to provide a PLL synthesizer circuit that can shorten lock-up time by automatically adjusting the short-circuit time of the LPF by the switching circuit according to the pull-in time of the LPF.

[Means to solve the problem]

FIG. 1 is a diagram explaining the principle of the present invention. That is, PLL
The synthesizer circuit performs voltage control on the voltage signal output from the PLL control unit 12 via the low-pass filter 5 based on the frequency and phase difference between the setting signal and the output signal of the voltage controlled oscillator 6 based on the set frequency from the outside. The output signal is output to the oscillator 6 to match the output signal frequency of the voltage controlled oscillator 6 with the set frequency, and a phase difference signal based on the phase difference between the set signal and the output signal of the voltage controlled oscillator 6 is PL.
A lock detection circuit 9 is provided which receives the signal from the L control section 12 and outputs an unlock signal when the phase difference is above a predetermined value, and outputs a lock signal when the phase difference is below a predetermined value. Then, the switching circuit 8 is closed based on the unlock signal of the lock detection circuit 9 and opened based on the lock signal.
It is connected in parallel with the low-pass filter 5 between the L control section 12 and the voltage controlled oscillator 6.

[For production]

The open/close circuit 8 is closed while the lock detection circuit outputs the unlock signal, shorting the PLL control section 12 and the voltage controlled oscillator 6.

〔Example〕

An embodiment of a PLL synthesizer circuit embodying the present invention will be described below with reference to FIGS. 2 to 4. Incidentally, the same components as those of the conventional example are given the same numbers and the explanation thereof will be omitted.

The embodiment of the present invention shown in FIG. 2 has the same configuration as the conventional example except that the lock detection circuit 9 is connected to the analog switch 8. The analog switch 8 is closed only when the unlock signal is output from the lock detection circuit 9.

The specific configuration of the charge pump 4, LPF 5, and analog switch 8 will be explained according to FIG. The PLL calculation unit l has a CMOS configuration. Further, the analog switch 8 is composed of a pair of MOS transistors 10 and an inverter 11. Then, such an analog switch 8, charge pump 4,
Is the phase comparator 3 and PLL calculation unit 1 BiCMOS? The LPF 5 and VCO 6 are external circuits. Note that the lock detection circuit 9 is also a commonly used and known circuit.

Now, in the PLL synthesizer circuit configured as described above, when the set frequency data DA by external input is raised as shown in FIG. Rise.

At the same time, the output signal Δf output from the phase comparator 3 becomes a pulse signal based on the phase difference between the setting signal fr and the feedback signal fp inputted to the phase comparator 3. Then, the mouth/socket detection circuit 9 receives the unlock signal SG″4 at L level.
is output to the analog switch 8, and the analog switch 8 is closed based on the output signal SG4, the charge pump 4 and the VCO 6 are short-circuited, and the output signal SG3 of the VCO 6 is output to the charge pump 4. As the DC level of the output signal SGI rises, its frequency rises, and this state is the setting that is input to the phase comparator 3.
This continues until the phase difference between the signal "qfr" and the feedback signal fp decreases to a predetermined value or less. Note that FIG. 6 shows a waveform diagram that is more expanded in the time axis direction than FIG. 4.

Therefore, if the phase difference between the setting signal fr input to the phase comparator 3 and the feedback signal fp is greater than a predetermined value, the analog switch 8 is automatically kept closed, so that the VCO
The output signal SG3 of charge pump 6 is converted to the output signal SG of charge pump 4.
It is possible to shorten the lock-up time by quickly following up the strobe signal STB, and there is no need to adjust the pulse width of the strobe signal STB in accordance with the pull-in time of the LPF 5.

〔Effect of the invention〕

As detailed above, the present invention provides an LPF using a switching circuit.
The short-circuit time of the PLL synthesizer circuit is automatically adjusted according to the pull-in time of the LPF, thereby achieving an excellent effect of shortening the lock-up time of the PLL synthesizer circuit.

[Brief explanation of drawings]

FIG. 1 is a diagram explaining the principle of the present invention, FIG. 2 is a block diagram showing a PLL synthesizer circuit according to an embodiment of the present invention, and FIG. 3 is a circuit diagram showing a specific configuration of a part of the PLL synthesizer circuit. FIG. 4 is a waveform diagram showing the operation of the PLL synthesizer circuit, FIG. 5 is a block diagram of the conventional PLL synthesizer circuit, and FIG. 6 is a waveform diagram showing the operation of the conventional PLL synthesizer circuit. In the figure, 5 is a low pass filter (LPF), 6 is a voltage controlled oscillator (VCO), 8 is an opening/closing circuit (analog switch), 9 is a lock detection circuit, and 12 is a PL, L control section. Fig. 1 Original fill diagram of the present invention Fig. 3 Part II showing an actual example of the present invention Fig. 11

Claims (1)

[Claims] 1. The voltage signal output from the PLL control unit (12) is low-passed based on the frequency and phase difference between the setting signal based on the external setting frequency and the output signal of the voltage controlled oscillator (6). The signal is outputted to the voltage controlled oscillator (6) via the filter (5) so that the output signal frequency of the voltage controlled oscillator (6) matches the set frequency, and the set signal and the output signal of the voltage controlled oscillator (6) are A lock detection device that receives a phase difference signal based on the phase difference between the A PLL synthesizer circuit comprising a circuit (9), an opening/closing circuit (8) that closes based on the unlock signal of the lock detection circuit (9) and opens based on the lock signal.
A PLL synthesizer circuit characterized in that a PLL synthesizer circuit is connected in parallel with the low-pass filter (5) between a PLL control section (12) and a voltage-controlled oscillator (6).