JPH0513541B2 - - Google Patents

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Publication number
JPH0513541B2
JPH0513541B2 JP24893386A JP24893386A JPH0513541B2 JP H0513541 B2 JPH0513541 B2 JP H0513541B2 JP 24893386 A JP24893386 A JP 24893386A JP 24893386 A JP24893386 A JP 24893386A JP H0513541 B2 JPH0513541 B2 JP H0513541B2
Authority
JP
Japan
Prior art keywords
amplifier circuit
stage amplifier
semiconductor chip
earth
ground
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP24893386A
Other languages
Japanese (ja)
Other versions
JPS63102350A (en
Inventor
Hiroyuki Ooike
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP24893386A priority Critical patent/JPS63102350A/en
Publication of JPS63102350A publication Critical patent/JPS63102350A/en
Publication of JPH0513541B2 publication Critical patent/JPH0513541B2/ja
Granted legal-status Critical Current

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  • Semiconductor Integrated Circuits (AREA)

Description

【発明の詳細な説明】 (イ)産業上の利用分野 本発明は例えばオーデイオ用アンプ回路等のよ
うに、多段縦続接続された増幅回路を内蔵した半
導体集積回路(IC)の改良に関する。
DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to an improvement in a semiconductor integrated circuit (IC) incorporating a multi-stage cascaded amplifier circuit, such as an audio amplifier circuit.

(ロ) 従来の技術 従来より、例えば第2図に示す如き縦続接続さ
れた大信号系の出力段増幅回路1と小信号系の前
段増幅回路2とを内蔵したICにおいては、電位
降下による回路間の影響を防ぐ各々に独立したア
ースパツドを設ける手法が例えば特願昭60−
176217号に記載されている。同図において、3は
入力端子、4は出力端子、5はVcc端子であり、
入力端子3に印加された入力信号を前段増幅回路
2で電圧増幅し、SEPP(シングルエンドプツシ
ユプル)から成る出力段増幅回路1で電流増幅し
て出力端子4に接続される負荷を駆動するように
構成されている。そして出力段増幅回路1と前段
増幅回路2とでアースの電位を共通すると、出力
段増幅回路1で増幅された信号電流によつてアー
スの配線に電位降下が生じ、これが前段増幅回路
2に帰還されて発振等の不都合を生じることにな
るのである。
(b) Prior Art Conventionally, for example, in an IC that incorporates a large signal system output stage amplifier circuit 1 and a small signal system front stage amplifier circuit 2 connected in cascade as shown in FIG. For example, a method of providing independent earth pads for each to prevent the influence of
Described in No. 176217. In the same figure, 3 is an input terminal, 4 is an output terminal, 5 is a Vcc terminal,
The input signal applied to the input terminal 3 is voltage amplified by the pre-stage amplifier circuit 2, and the current is amplified by the output stage amplifier circuit 1 consisting of SEPP (single-ended push-pull) to drive the load connected to the output terminal 4. It is configured as follows. When the output stage amplifier circuit 1 and the pre-stage amplifier circuit 2 share a common ground potential, a potential drop occurs in the ground wiring due to the signal current amplified by the output stage amplifier circuit 1, and this is returned to the pre-stage amplifier circuit 2. This causes problems such as oscillation.

第3図は斯る構造のICを示す平面図で、6は
半導体チツプ、7,8は第1、第2のアースパツ
ド、9,10は第1、第2のアース電極である。
半導体チツプ6の表面には所定のプロセスによつ
て第2図の回路が2チヤンネル分組み込まれ、回
路を構成するとトランジスタは夫々分離領域で囲
まれて分離される。そして出力段増幅回路1の周
囲を囲むように第1アース電極9が設けられ、且
つその下の分離領域とオーミツクコンタクトする
ことにより、大電流を扱う出力トランジスタの寄
生電流を直ちに吸い出すように構成している。ま
た、前段増幅回路2の近傍には第2アース電極1
0が設けられ、半導体チツプ6とは電気的に独立
して前段増幅回路2にアース電位を供給する。そ
して上述した理由より、第1、第2のアース電極
9,10夫々に独立した第1、第2のアースパツ
ド7,8を設け、外部接続用の端子としている。
FIG. 3 is a plan view showing an IC having such a structure, in which 6 is a semiconductor chip, 7 and 8 are first and second earth pads, and 9 and 10 are first and second earth electrodes.
Two channels of the circuit shown in FIG. 2 are incorporated into the surface of the semiconductor chip 6 by a predetermined process, and when the circuit is constructed, the transistors are surrounded and isolated by isolation regions. A first ground electrode 9 is provided to surround the output stage amplifier circuit 1, and is configured to immediately suck out the parasitic current of the output transistor that handles a large current by making ohmic contact with the isolation region below it. are doing. In addition, a second ground electrode 1 is provided near the front stage amplifier circuit 2.
0 is provided, and supplies a ground potential to the front stage amplifier circuit 2 electrically independently from the semiconductor chip 6. For the reasons mentioned above, independent first and second ground pads 7 and 8 are provided for the first and second ground electrodes 9 and 10, respectively, to serve as terminals for external connection.

(ハ) 発明が解決しようとする問題点 しかしながら、従来の半導体集積回路では出力
段増幅回路1や前段増幅回路2の寄生電流の全て
を第1アース電極9のみで吸い出す為、寄生電流
によつて半導体チツプ6に電位勾配が発生し、前
段増幅回路2部において発振や寄生サイリスタ等
の不都合を生じる欠点があつた。
(C) Problems to be Solved by the Invention However, in the conventional semiconductor integrated circuit, all of the parasitic current of the output stage amplifier circuit 1 and the pre-stage amplifier circuit 2 is sucked out only by the first earth electrode 9, so that the parasitic current is There is a drawback that a potential gradient occurs in the semiconductor chip 6, causing problems such as oscillation and parasitic thyristors in the front stage amplifier circuit 2.

(ニ) 問題点を解決するための手段 本発明は斯上した欠点に鑑みてなされ、前段増
幅回路2を形成した領域の半導体チツプ6とオー
ミツクコンタクトし且つ出力段増幅回路1が形成
された領域の半導体チツプ6とはオーミツクコン
タクトせず半導体チツプ6上を延在して第1アー
スパツド7に接続する第3のアース電極11を設
けることにより、従来の欠点を大幅に改善した半
導体集積回路を提供するものである。
(d) Means for Solving the Problems The present invention has been made in view of the above-mentioned drawbacks, and the output stage amplifier circuit 1 is formed in ohmic contact with the semiconductor chip 6 in the region where the front stage amplifier circuit 2 is formed. This is a semiconductor integrated circuit in which the drawbacks of the conventional semiconductor integrated circuit are greatly improved by providing a third ground electrode 11 that does not make ohmic contact with the semiconductor chip 6 in the region but extends over the semiconductor chip 6 and connects to the first ground pad 7. It provides:

(ホ) 作用 本発明によれは、前段増幅回路2付近の寄生電
流を直ちに第3のアース電極11で吸い出すこと
ができ、しかも第3のアース電極11を第1アー
スパツド7に接続することによつて他に全く影響
を与えずに半導体チツプ6の電位を安定にするこ
とができる。
(E) Effect According to the present invention, the parasitic current near the front stage amplifier circuit 2 can be immediately sucked out by the third earth electrode 11, and moreover, by connecting the third earth electrode 11 to the first earth pad 7. Therefore, the potential of the semiconductor chip 6 can be stabilized without affecting anything else.

(ヘ) 実施例 以下、本発明を図面を参照しながら詳細に説明
する。
(f) Examples Hereinafter, the present invention will be explained in detail with reference to the drawings.

第1図は本発明の半導体集積回路を示す平面図
で、6は半導体チツプ、7,8は第1、第2のア
ースパツド、9,10,11は第1乃至第3のア
ース電極である。半導体チツプ6の表面には所定
のプロセスによつて第2図の回路が2チヤンネル
分上下対象になるように作り込まれ、前段増幅回
路2を構成するトランジスタ及び出力段増幅回路
1のSEPPを構成するパワートランジスタは夫々
分離領域で囲まれて分離される。個々に分離され
たトランジスタは電極配線によつて所定の機能を
果すように接続され、半導体チツプ6の外周部付
近には外部接続用の互いに独立した第1、第2の
アースパツド7,8が配置される。そして各チヤ
ンネルの出力段増幅回路1の領域を各々囲むよう
にその下の分離領域とコンタクトホール12を介
してオーミツクコンタクトする第1アース電極9
が設けられ、大電流を扱う出力段増幅回路1の寄
生電流を直ちに回収するように構成されて更に第
1アースパツド7に接続される。また、前段増幅
回路2の近傍には半導体チツプ6とは電気的に独
立した第2アース電極10が延在し、第2アース
パツド8に接続される。
FIG. 1 is a plan view showing a semiconductor integrated circuit of the present invention, in which 6 is a semiconductor chip, 7 and 8 are first and second earth pads, and 9, 10, and 11 are first to third earth electrodes. The circuit shown in FIG. 2 is fabricated on the surface of the semiconductor chip 6 by a predetermined process so that two channels are vertically symmetrical, and the transistors forming the front-stage amplifier circuit 2 and the SEPP of the output-stage amplifier circuit 1 are formed. The power transistors are surrounded and isolated by isolation regions. The individual transistors are connected to each other by electrode wiring so as to perform a predetermined function, and first and second ground pads 7 and 8, which are independent of each other for external connection, are arranged near the outer periphery of the semiconductor chip 6. be done. A first ground electrode 9 is in ohmic contact with the isolation region therebelow via the contact hole 12 so as to surround the region of the output stage amplifier circuit 1 of each channel.
is connected to the first earth pad 7 and is configured to immediately recover the parasitic current of the output stage amplifier circuit 1 which handles a large current. Further, a second ground electrode 10 that is electrically independent of the semiconductor chip 6 extends near the front stage amplifier circuit 2 and is connected to a second ground pad 8.

そして本発明の特徴とする第3のアース電極1
1が、前段増幅回路2が形成された領域の近傍で
分離領域を介して半導体チツプ6とオーミツクコ
ンタクトをなし、出力段増幅回路1の領域を半導
体チツプ6とはオーミツクコンタクトせずに横断
して第1アースパツド7に接続される。
And the third earth electrode 1 which is a feature of the present invention
1 makes ohmic contact with the semiconductor chip 6 via the isolation region near the region where the pre-stage amplifier circuit 2 is formed, and crosses the region of the output stage amplifier circuit 1 without making ohmic contact with the semiconductor chip 6. and is connected to the first earth pad 7.

斯る構成によれば、第3のアース電極11によ
つて前段増幅回路2が形成された領域における半
導体チツプ6の寄生電流を効果的に吸出すること
ができ、さらに他の回路へ全く影響を与えること
が無い。
According to such a configuration, the parasitic current of the semiconductor chip 6 in the region where the front-stage amplifier circuit 2 is formed can be effectively sucked out by the third ground electrode 11, and furthermore, the parasitic current can be sucked out completely by the third ground electrode 11. I have nothing to give.

即ち、前段増幅回路2は高利得で設計されるの
が普通であり、吸出した寄生電流によつてアース
電位が不安定になるのは避けなけならないから、
前段増幅回路2が形成された領域の寄生電流を第
2アース電極10で吸出すことは出来ない。一
方、第1のアース電極9を延長して前段増幅回路
2付近でオーミツクコンタクトされると、第1の
アース電極9のインピーダンスと大電流を吸う出
力段増幅回路1の寄生電流によつてかなり大きな
電位降下が発生し、前段増幅回路2付近の半導体
チツプ6の電位を不安定にして発振等を招き易く
なる。これに対して本発明によれば、前段増幅回
路2付近の寄生電流は出力段増幅回路1付近の寄
生電流に比べれば極く僅かであるから第3のアー
ス電極11自身の電位も降下も極く僅かであり、
しかも第1のアースパツド7以降は低インピーダ
ンスの金属細線と外部リードによつて吸出される
ので、第1のアース電極9が吸出した寄生電流に
よつて影響されること無く、前段増幅回路2付近
の半導体チツプ6の電位を安定にせしめ、回路の
発振や寄生サイリスタの発生等を未然に防げこと
ができる。また、出力段増幅回路1付近の半導体
チツプ6とは独立しているので、大電流を扱う出
力段増幅回路1の寄生電流には何等影響を受けな
い。尚、出力段増幅回路1が扱う電流がかなり大
きく、金属細線のインピーダンスをも問題になる
ようであれば、第3のアース電極11専用に独立
したグランドパツドを設ける手法も考えられる。
更にまた、第3のアース電極11を上下線対象と
なるよう、第1、第2チヤネルの領域の略中央に
配設することによつて各チヤネルにおける半導体
チツプ6の電位がアンバランスになることを防い
でいる。このことは第1、第2アース電極9,1
0についても同様であり、そのため第1、第2ア
ースパツド7,8は第1、第2アース電極9,1
0が上下線対象となるよう、それらの中央に配設
されている。
That is, the preamplifier circuit 2 is normally designed with a high gain, and it is necessary to avoid the ground potential becoming unstable due to the parasitic current sucked out.
The parasitic current in the region where the preamplifier circuit 2 is formed cannot be sucked out by the second earth electrode 10. On the other hand, if the first earth electrode 9 is extended and ohmic contact is made near the front stage amplifier circuit 2, the impedance of the first earth electrode 9 and the parasitic current of the output stage amplifier circuit 1 which sucks a large current will cause a considerable A large potential drop occurs, which destabilizes the potential of the semiconductor chip 6 near the front stage amplifier circuit 2, making it easy to cause oscillations and the like. On the other hand, according to the present invention, since the parasitic current near the front stage amplifier circuit 2 is extremely small compared to the parasitic current near the output stage amplifier circuit 1, the potential and drop of the third earth electrode 11 itself are extremely small. very few,
In addition, since the air from the first earth pad 7 onwards is drawn out by the low impedance thin metal wire and the external lead, it is not affected by the parasitic current sucked out by the first ground electrode 9, It is possible to stabilize the potential of the semiconductor chip 6 and prevent circuit oscillation and generation of parasitic thyristors. Further, since it is independent from the semiconductor chip 6 near the output stage amplifier circuit 1, it is not affected by the parasitic current of the output stage amplifier circuit 1, which handles a large current. Incidentally, if the current handled by the output stage amplifier circuit 1 is quite large and the impedance of the thin metal wire becomes a problem, a method of providing an independent ground pad exclusively for the third earth electrode 11 may also be considered.
Furthermore, by arranging the third ground electrode 11 approximately in the center of the first and second channel regions so as to be symmetrical with respect to the upper and lower lines, the potential of the semiconductor chip 6 in each channel becomes unbalanced. is prevented. This means that the first and second earth electrodes 9, 1
The same applies to 0, so the first and second ground pads 7 and 8 are connected to the first and second ground electrodes 9 and 1.
0 is placed in the center of these lines so that they are symmetrical.

(ト) 発明の効果 以上説明した如く、本発明によれは第3のアー
ス電極11によつて前段増幅回路2が形成された
領域における半導体チツプ6の寄生電流を効果的
に吸出すことができるので、前段増幅回路2の領
域の半導体チツプ6の電位を安定にして回路の発
振や寄生サイリスタの発生等を未然に防げる利点
を有する。さらに、第3のアース電極11を直接
第1のアースパツド7に接続することによつて、
前段増幅回路2の寄生電流を吸出す際に他の回路
への影響を完全に無くすことができる利点をも有
する。
(g) Effects of the Invention As explained above, according to the present invention, the parasitic current of the semiconductor chip 6 in the region where the front-stage amplifier circuit 2 is formed can be effectively sucked out by the third earth electrode 11. Therefore, there is an advantage that the potential of the semiconductor chip 6 in the region of the preamplifier circuit 2 can be stabilized, thereby preventing circuit oscillation and generation of parasitic thyristors. Furthermore, by connecting the third earth electrode 11 directly to the first earth pad 7,
It also has the advantage of being able to completely eliminate the influence on other circuits when sucking out the parasitic current of the preamplifier circuit 2.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の半導体集積回路装置を示す平
面図、第2図は一般的な増幅回路を示す回路図、
第3図は従来の半導体集積回路装置を示す平面図
である。 1は大信号系の出力段増幅回路、2は小信号系
の前段増幅回路、6は半導体チツプ、7,8は第
1、第2のアースパツド、9乃至11は第1乃至
第3のアース電極である。
FIG. 1 is a plan view showing a semiconductor integrated circuit device of the present invention, FIG. 2 is a circuit diagram showing a general amplifier circuit,
FIG. 3 is a plan view showing a conventional semiconductor integrated circuit device. 1 is a large signal system output stage amplifier circuit, 2 is a small signal system front stage amplifier circuit, 6 is a semiconductor chip, 7 and 8 are first and second earth pads, and 9 to 11 are first to third earth electrodes. It is.

Claims (1)

【特許請求の範囲】[Claims] 1 出力段増幅回路及びその前段に設けられた前
段増幅回路と、前記出力段増幅回路のパワートラ
ンジスタを囲むように半導体チツプとオーミツク
コンタクトした第1アース電極と、前記前段増幅
回路に接地電位を印加する第2アース電極と、前
記第1アース電極と接続した外部接続用の第1ア
ースパツドと、前記第2アース電極と接続した外
部接続用の第2アースパツドとを具備した半導体
集積回路装置において、前記前段増幅回路が形成
された領域のみで前記半導体チツプとオーミツク
コンタクトし且つ前記半導体チツプ上を延在して
前記第1アースパツドに接続した第3アース電極
を設けたことを特徴とする半導体集積回路装置。
1. A ground potential is applied to the output stage amplifier circuit, the front stage amplifier circuit provided in front of the output stage amplifier circuit, a first ground electrode that is in ohmic contact with the semiconductor chip so as to surround the power transistor of the output stage amplifier circuit, and the front stage amplifier circuit. A semiconductor integrated circuit device comprising a second earth electrode for applying voltage, a first earth pad for external connection connected to the first earth electrode, and a second earth pad for external connection connected to the second earth electrode, A semiconductor integrated circuit characterized in that a third ground electrode is provided which is in ohmic contact with the semiconductor chip only in the region where the pre-stage amplifier circuit is formed, extends over the semiconductor chip, and is connected to the first ground pad. circuit device.
JP24893386A 1986-10-20 1986-10-20 Semiconductor integrated circuit device Granted JPS63102350A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24893386A JPS63102350A (en) 1986-10-20 1986-10-20 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24893386A JPS63102350A (en) 1986-10-20 1986-10-20 Semiconductor integrated circuit device

Publications (2)

Publication Number Publication Date
JPS63102350A JPS63102350A (en) 1988-05-07
JPH0513541B2 true JPH0513541B2 (en) 1993-02-22

Family

ID=17185573

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24893386A Granted JPS63102350A (en) 1986-10-20 1986-10-20 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS63102350A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101866227B1 (en) * 2016-07-29 2018-07-19 주식회사 세야 Head Up Display Unit Assembly Jig for Vehicle

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200518345A (en) * 2003-08-08 2005-06-01 Renesas Tech Corp Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101866227B1 (en) * 2016-07-29 2018-07-19 주식회사 세야 Head Up Display Unit Assembly Jig for Vehicle

Also Published As

Publication number Publication date
JPS63102350A (en) 1988-05-07

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