JPH0523067B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a semiconductor integrated circuit, and particularly to an improvement of a semiconductor integrated circuit incorporating a two-channel amplifier circuit.

(b) Prior Art Due to the structure of semiconductor integrated circuits, it is difficult to form high-voltage transistors, and when forming an amplifier circuit, it is often used to increase the output by using a BTL connection. As such a known document, BTL connection is described on page 189 of "Stereo Reproduction Device", written by Ken Suzuki, published by Nikkan Kogyo Shimbun (November 1971).

Generally, BTL connections are the output split type (Figure 3) and the NF floating type (Figure 4) explained below.
There is. In the output split type BTL connection, an input signal is applied to the input terminal IN of the non-inverting amplifier 31, the feedback terminal NF is grounded via a capacitor, and the output terminal
Output signal is obtained from OUT. On the other hand, the input terminal IN of the inverting amplifier 32 is grounded, and the output signal of the non-inverting amplifier 31 is fed back to the feedback terminal NF via a dividing resistor and a capacitor. and load R _L
is connected between the output terminals of both amplifiers 31 and 32 to obtain twice the output signal.

In the NF floating type BTL connection, an input is applied to the input terminal IN of the non-inverting amplifier 31, the input terminal IN of the inverting amplifier 32 is grounded, and both amplifiers 31,
32's feedback terminal NF is connected with a capacitor and a resistor, and a load R _L is connected between the output terminals OUT of both amplifiers 31 and 32.

In a semiconductor integrated circuit incorporating a two-channel amplifier circuit with the BTL connection described above,
As shown in FIG. 5, the output transistors of the amplifier circuits of each channel are formed. The output transistor of the first channel amplifier circuit is formed in the upper half of the chip, and the output transistor of the second channel amplifier circuit is formed in the lower half of the chip.
The output transistor of the first channel is formed by two NPN transistors 41 and 42 arranged on the left and right, and these transistors 41 and 42 are connected to form an SEPP (single-ended push-pull). The collector electrode 43 of the NPN transistor 41 on the left side is connected to the Vcc power supply electrode 44, the base electrode 45 is connected to the amplification circuit at the previous stage, and the emitter electrode 46 is connected to the output terminal 47 of the first channel. The collector electrode 48 of the NPN transistor 42 on the right side is the output terminal 47 of the first channel.
The base electrode 49 is connected to the amplifying circuit at the previous stage, and the emitter electrode 50 is connected to the ground electrode 51.
It is connected to the. Note that the output transistor of the second channel is also formed line-symmetrically with the first channel. The equivalent circuit is shown in FIG.

In such a semiconductor integrated circuit, the output transistors of each channel are surrounded and isolated by isolation regions,
A ground electrode 51 in ohmic contact with the isolation region is provided on the isolation region at the right end of the chip, and the power supply electrode 4
4 was formed commonly for both channels.

(c) Problems to be Solved by the Invention However, in such a semiconductor integrated circuit, the ground electrode 51 is contacted only in the isolation region at the right end of the chip. It had the disadvantage that it could not be sucked out sufficiently and was likely to cause parasitic effects.

(d) Means for Solving the Problems The present invention has been made in view of these drawbacks, and by surrounding the output transistor of each channel with a ground electrode 51, a semiconductor integrated circuit has been realized which greatly improves the conventional drawbacks. It is intended to.

(E) Effect According to the present invention, by surrounding the output transistor of each channel with the ground electrode 51, the leakage current from the output transistor can be immediately sucked out by the ground electrode 51 which is electrically connected to the substrate, and parasitic effects can be prevented. be.

(f) Embodiment An embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.

The semiconductor integrated circuit according to the present invention is formed by incorporating a two-channel amplifier circuit, and the output transistor of the amplifier circuit of each channel is formed as shown in FIG. That is, the first channel amplifier circuit is formed in the upper half of the chip and consists of the first channel small signal circuit located on the left side and the output transistor located on the right side, and the second channel amplifier circuit has a similar arrangement. It is formed in the lower half of the chip. The output transistor of the first channel is formed by two NPN transistors 1 and 2 arranged on the left and right.
Connected to form SEPP (Single End Push Pull). Each transistor has a plurality of base regions 4 and emitter regions 5 formed in a collector region 3 shown by solid lines, and desired connections are made by electrodes shown by dotted lines. The collector electrode 6 of the NPN transistor 1 on the left is the first Vcc power supply electrode 7
The base electrode 8 is connected to a small signal amplifier circuit at the previous stage, and the emitter electrode 9 is connected to an output terminal 10 of the first channel. Right
The collector electrode 11 of the NPN transistor 2 is the first
The base electrode 12 is connected to the output terminal 10 of the channel, and the base electrode 12 is connected to the amplification circuit of the small signal system in the previous stage.
The emitter electrode 13 is connected to a ground electrode 14 common to both channels. Note that the output transistor of the second channel is also formed line-symmetrically with the first channel.

A feature of the present invention lies in the arrangement of the ground electrode 14. The output transistors of each channel are surrounded and separated by isolation regions, and the ground electrode 14 surrounds three sides of the output transistor of each channel. These three sides are the three sides excluding the upper side of the output transistor of the first channel and the lower side of the output transistor of the second channel. Ground electrode 14
is in ohmic contact with the isolation region below it, and extends between them by dividing the conventionally common Vcc power supply electrode. Note that the wiring from the first and second Vcc power supply electrodes 10, 15 to the small signal circuits for each channel adopts a cross wiring structure as shown in FIG. In FIG. 2, 20 is a P type semiconductor substrate, 21 is a P ₊ type isolation region diffused into an N type epitaxial layer, 22 is an oxide film, 14 is a ground electrode, 7 and 15 are first and second This is the Vcc power supply electrode. With the above structure, the ground electrode 14 is connected to all three sides via cross wiring, and the ground electrode 14 provided at the right end of the chip is connected to an external pin via a bonding wire. Furthermore, since the large-area separation region 21 under the first and second Vcc power supply electrodes 7 and 15 is used as a cross wiring, a conductive path with considerably low resistance can be formed, and the separated ground electrodes 14 can be connected with low resistance. There is. Note that the first and second wires are connected to the cross wiring part.
Wiring lines are formed from the 2Vcc power supply electrodes 7 and 15 to the small signal circuits of each channel.

According to the structure of the present invention described above, the output transistors of each channel, that is, the two NPN transistors 1 and 2, are surrounded by the ground electrode 14 on three sides excluding the top or bottom side. Leakage current from the ground electrode 14 is immediately sucked out through the isolation region to the ground electrode 14.

Note that the side where the ground electrode 14 is not provided is adjacent to the top or bottom side of the chip, so there is little risk of leakage current flowing to the small signal circuit, and the wiring to the preceding small signal circuit is derived from this side. .

(g) Effects of the Invention According to the present invention, the power supply electrode is divided and three sides of the output transistor of each channel are connected to the ground electrode 14.
Since it is surrounded by , the leakage current of the output transistor can be immediately absorbed by the ground electrode 14, which has the advantage of preventing parasitic effects.

Further, since the wiring layer 16 from the power supply electrodes 7 and 15 and the ground electrode 14 have a cross wiring structure, the output transistor of each channel can be surrounded by the ground electrode 14 regardless of other wiring.
It has the advantage of fewer design restrictions.

Furthermore, the present invention has the advantage that since the cross wiring is formed in the separated region under the first and second power supply electrodes 7 and 15, no extra space is required and an increase in pattern area can be prevented.

Furthermore, the present invention has the advantage that a BTL-connected two-channel amplifier circuit can be stably obtained, and the range of application of semiconductor integrated circuits can be greatly expanded.

[Brief explanation of the drawing]

Fig. 1 is a top view illustrating a semiconductor integrated circuit according to the present invention, Fig. 2 is a sectional view illustrating a cross wiring structure used in the present invention, and Figs. 3 and 4 are illustrating general BTL connections. 5 is a top view illustrating a conventional semiconductor integrated circuit, and FIG. 6 is a circuit diagram illustrating a conventional semiconductor integrated circuit.
FIG. 2 is an equivalent circuit diagram of FIG. Explanation of main figure numbers, 1 and 2 are NPN transistors,
7 is the first Vcc power supply electrode, 10 is the output terminal of the first channel, 14 is the ground electrode, and 15 is the second
Vcc power supply electrode.

Claims (1)

[Claims] 1. In a semiconductor integrated circuit incorporating a two-channel amplifier circuit including an output transistor constituting a SEPP (single-ended push-pull) circuit, three of the two output transistors of each amplifier circuit
A ground electrode is provided in ohmic contact with the separation region so as to surround the sides, a power supply electrode common to the two output transistors of each amplifier circuit is divided by the ground electrode, and the ground electrode is divided by a wiring line from the power supply electrode. What is claimed is: 1. A semiconductor integrated circuit characterized in that the semiconductor integrated circuit is connected in a crossover manner using a separation region provided under a power supply electrode.