JPH051477B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a display controller that can draw both still images and moving images on a display screen.

[Prior Art] In recent years, video game machines and other graphic display devices have used display controllers that can display both moving images and still images. Video processing in this type of display controller is generally 8
A moving image pattern of approximately 8 pixels is used as a display unit, and these moving image patterns are moved singly or in combination.

By the way, in the conventional display controller, the color of the movement pattern is a single color for each pattern, and therefore the display screen inevitably becomes monotonous.

[Object of the Invention] This invention was made in view of the above-mentioned circumstances, and its purpose is to be able to draw a moving image pattern with a complex color scheme, thereby significantly improving the expressive ability on the display screen. The purpose of the present invention is to provide a display controller that can be improved.

[Features of the invention] A plurality of video control tables storing information specifying one of the video patterns and information determining the display position of the specified video pattern, and a plurality of video control tables provided corresponding to these video control tables. , a plurality of storage blocks in which color codes specifying colors for each horizontal line of data constituting the video pattern are stored, and color display of the video pattern is controlled based on the video control table and the contents of the storage block. The present invention is characterized by comprising a moving image color control means.

[Example] Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1A is a block diagram showing the configuration of an embodiment of the present invention, and in the figure, numeral 1 indicates a display controller according to this embodiment. 2 is
CPU, 3 is memory consisting of ROM in which programs used by CPU 2 are stored and RAM for data storage, 4 is VRAM (video RAM), 5 is
It is a CRT display device. In this case, the VRAM 4 has a still image pattern table 4 in which still image patterns (dot patterns) are stored, as shown in FIG.
a, a still image position table 4b in which the position at which a still image pattern should be displayed is stored, a still image color table 4c in which the color of each still image pattern is stored as a color code (4 bits), and a still image color table 4c in which a plurality of moving image patterns are stored. A video pattern table 4d to be stored,
A moving image control table group 4e in which coordinates for displaying moving image patterns and the like are stored, and a moving image color table 4f in which color codes of moving image patterns are stored are provided. Video pattern table 4d
As shown in Figure 3, one video pattern is stored every 8 bytes, and each video pattern has a different name (in the figure, "0" to
An 8-bit name (indicated by “255”) is set. As an example, the video pattern stored in the pattern name "n" is shown enlarged in the figure. In the figure, the part with data "1" is the pattern part, and the part with data "0" is the background part (transparent part). be. Further, as shown in FIG. 4A, the video control table group 4e consists of 32 video control tables each having a length of 4 bytes, and each video control table is numbered from 0 to 31 in order from the lowest address. There is. here,
The contents of the moving image control table No. k (same as the moving image display tables of other numbers) are shown enlarged in the figure. The 0th and 1st bytes shown in the figure store the Y and X coordinates of the position where the moving image pattern should be displayed (the upper left end position of the moving image pattern is the reference position of the moving image).
Therefore, when the data in the 0th and 1st bytes are rewritten, the moving image moves on the screen. and,
The second byte stores the name of the moving image pattern to be displayed, and the third byte is unused.
Next, the moving image color table 4f consists of 32 8-byte long memory blocks as shown in FIG. 4B, and these memory blocks BC0 to BC
31 are provided corresponding to moving image display tables No. 0 to No. 31, respectively. Here, the memory block is shown in the same figure.
Indicates the memory contents of BCk (k is 0 to 31). As shown in the figure, the lower 4 bits of the 0th to 7th bytes of the memory block BCk contain color codes that specify the colors of the 0th to 7th bytes of the moving image pattern specified by the No. k moving image display table. remembered. In other words, the data “1” in the 0th byte of the video pattern
The color is specified by the color code in the 0th byte of the memory block BCk, and similarly, the data "1" part of the 1st to 7th bytes of the video pattern are the 1st to 7th bytes of the memory block BCk. Each color is designated by the color code within.

Next, each component of the display controller 1 will be explained. In FIG. 1A, the timing signal generation circuit 8 generates basic clock pulses using an internally provided crystal oscillator, and also
A dot clock pulse DCP and a synchronization signal SYNC are generated based on this basic clock pulse.
Then, the dot clock pulse DCP is sent to the clock terminal CK of the horizontal counter 9, and the synchronization signal
SYNC is output to each CRT display device 5. Here, the dot clock pulse DCP is a clock pulse corresponding to each dot displayed on the CRT display screen. In other words, it is output in synchronization with the display timing of each dot that is sequentially displayed by horizontal scanning of the screen. This is the clock pulse. Also,
This timing signal generation circuit 8 generates various timing signals necessary for processing image data, and outputs them to the image data processing circuit 10.

The horizontal counter 9 is a 341-base up counter and is reset at the beginning of the screen display, and the signal HP is sent to the vertical counter 11 every time the dot clock pulse DCP is counted by 341 pulses.
output to clock terminal CK of The count output of the horizontal counter 9 indicates which dot from the left of the electron beam screen of the CRT display device 5 is being scanned. That is, for example, when the count output is "0", the electron beam is scanning at the leftmost end of the screen, and when it is [100], the electron beam is scanning the 101st dot position from the left of the screen.
In addition, in this example, one line horizontally on the screen
It is set to display 256 dots. Therefore, the count output of the horizontal counter 9 is "256" ~
The period "340" is a non-display period.

The vertical counter 11 is a 262-decimal up counter, and is initially reset at the start of screen display.

The count output of this vertical counter 11 is
It shows which line from the top of the screen of the CRT display device 5 is being scanned by the electron beam. Further, in this embodiment, the number of dots on the screen in the vertical direction is set to 192, so the period when the count output of the vertical counter 11 is between "192" and "261" is a non-display period.

The image data processing circuit 10 sequentially writes image data supplied from the CPU 2 via the interface circuit 12 into each table in the VRAM 4.
Then, after writing to VRAM4 is completed,
When a display command is output from the CPU 2, the image data processing circuit 10 outputs a still image pattern table 4a,
Each data in the still image position table 4b and the still image color table 4c is read out, and based on the read data, it is detected which color of still image dots should be displayed at each dot position on the CRT screen, and the horizontal counter 9 And the color code (4 bits) is sequentially applied from terminal TG according to the scanning position of the electron beam indicated by each count output of the vertical counter 11.
is output and supplied to the color palette 13. In addition, the image data processing circuit 10 also operates the moving image pattern table 4d in parallel with the above-described still image display operation.
and based on the data in the video control table group 4e, calculate and extract data necessary for video display,
The signal is supplied to the moving image processing circuit 15.

Here, the configuration of the still image data processing circuit 10 will be explained in detail.

FIG. 1B is a block diagram showing the configuration of the image data processing circuit 10. As shown in FIG. In the figure, bus CW (8
bit) is the bus for writing data from CPU2,
Bus CW (8 bits) is a bus for reading data from CPU2, bus AH (10 bits) and AL (8 bits).
is the address specification bus for VRAM4, and bus AH
specifies the upper 10 bits, and bus AL specifies the lower 8 bits. The bus VW is a bus for writing data to the VRAM 4, the bus VRL is a bus for reading data from the VRAM 4, and the bus Clr is a bus on which a color code is carried, and is connected to the color palette 13 shown in FIG.

Next, the register group B1 consists of registers B1a to B1e that store the start addresses of each table type. These registers B1a to B1e contain a still image position table 4b, a still image color table 4c, a still image pattern table 4a, a moving image control table 4e, and a moving image pattern table 4d.
Each start address of is stored and sent via bus CW.
It is now possible to rewrite from CPU2.
The color information register B2 stores two types of still image color codes read from the still image color table in the VRAM, and selects one of them according to the "1"/"0" signal output from the pattern shifter B3. is selectively output and placed on the color bus Clr.
The pattern shifter B3 is connected via the bus VRL.
This is a shift register that converts the still image data read from the VRAM 4 from parallel to serial, and its output "1"/"0" is used as color information and is supplied to the register B2 to determine the still image display color.

Next, the video number counter B4 stores the number K of each video control table (video number) and the storage address of the Y coordinate in this table (0th byte in this embodiment; see FIG. 4). In a 7-bit counter, the top 5 bits represent the video number K, and the bottom 2
Indicates whether the bit is an X or Y pattern name or color information, and the video control table group 4
When searching e to detect a moving image to be displayed on the next horizontal scanning line, the moving image number K is sequentially incremented. At this time, the lower two bits are always "0" and indicate only the Y coordinate of the video control table. During the display period, this search
The Y coordinate of each video control table is investigated and this is compared with the count value NV of the vertical counter 11. When a video to be displayed is detected, the content of the video number counter B4 at that time is set to the video number.
Register to FIFO.B5. In this case, video number k(0
- 31) in descending order of age, and once eight are registered, no further entries will be accepted. In this way, during the horizontal display period, up to eight video numbers k to be displayed on the next horizontal scanning line are registered in the video number FIFO.B5, and then these are sequentially read out during the horizontal non-display period to control each video. From the table to the video's Y and X coordinates,
This is the address used to read out the video pattern name, color code, CC, IC bit, etc. The data read from each video control table is then transferred to the video processing circuit 15 via the bus VRL.

Note that the ninth video number that was not entered into the video FIFO.B5 is registered in the register B6.

Next, the ALU (arithmetic unit) B7 compares the count value NV of the vertical counter 11 with the Y coordinate, calculates the address of the video image data, etc.
The calculation result is supplied to decoder B9 via status B8. The decoder B9 operates under the control of the mode register B10.
ROM (hereinafter referred to as μ program ROM) B11
It decodes the commands supplied from the bus and controls the sequence of data to be loaded on each bus. This μ program ROMB11 includes a horizontal counter 9,
A vertical counter 11 is connected to specify the read address of the instruction.

Next, the video processing circuit 15 is a circuit that controls the display of the video based on the supplied data, and detects the display timing of the video and adds the color code of the corresponding video to the color palette 13 based on this timing. Furthermore, when the video processing circuit 15 detects that there is no video data to be displayed, it outputs a still image display signal S2 (“1” signal).
is supplied to the image data processing circuit 10. The image data processing circuit 15 is configured to output a still image color code only when a still image display command signal S2 is supplied, and as a result, a still image and a moving image are displayed at a certain dot position on the display screen. If there is a conflict, the video will be displayed with priority. Note that details of the moving image processing circuit 15 will be described later.

Next, the color palette 13 is a kind of code conversion circuit, which converts the 4-bit color code into red color data RD, green color data GD, and blue color data BD (each of these color data is 3 bits) and sends them to the DAC. (Digital/analog converter) Output to 14. DAC14 converts the color data RD, GD, BD into analog signals to create RGB signals, and converts this RGB signal into analog signals.
Output to CRT display device 5. Here, FIG. 5 shows an example of the correspondence among color codes, color data, and display colors.

Next, a more specific configuration of the moving image processing circuit 15 will be explained.

FIG. 6 is a block diagram showing the configuration of the moving image processing circuit 15. In the figure, reference numerals 20 to 27 each designate a video processor, which are constructed in the same way and are supplied with video data in the VRAM 4 via the image data processing circuit 10. The configuration of this moving picture processor 20 (or 21 to 27) is shown in FIG. In the figure, 30 is an X counter to which the first byte data of the video control table of No. k (k is 0 to 31) shown in FIG. The transferred X coordinate data is counted down based on the clock pulse CK synchronized with the display timing of each dot that is sequentially displayed. 31
is an O detection circuit which outputs a "1" signal when the count output of the X counter reaches "0". 32
is a pattern shifter to which data (1 byte) within the address specified by the processing described later among the moving image patterns in the moving image pattern table 4d is transferred, and is based on the clock signal CK supplied via the AND gate 33. Then, the transferred pattern data is sequentially shifted from the most significant bit and output. The output signal of this pattern shifter 32 is output as a pattern signal SPPT. 35 is a color code register to which any one of the color codes in the memory block BCk (FIG. 4 B) is supplied, and the 0th to 3rd bits contain color codes C0 to C3.
is supplied. The color codes C0-C3 in the color code register 35 are supplied to the color palette 13 via three-state buffers 36-39, respectively. In this case, the pattern signal SPPT is applied to the buffers 36 to 39 as the opening/closing signal to the priority circuit 4.
0, and the signal SEPP is “1”
When it becomes "0", it is in the open state, and when it becomes "0", it is in the closed state.
The priority circuit 40 is a circuit that sets priorities for the video processors 20 to 27 in the order of video processors 20, 21, . This is a circuit that inhibits the signal SPPT of a low-speed video processor.

Next, the operation of this embodiment will be explained.

FIG. 8 is a diagram showing the relationship between the display screen in this embodiment and the line of the electron beam that operates this screen.
It is divided into DS #31 display sections. and,
Eight dots are drawn horizontally in one display section, and while these eight dots are being drawn, the image data processing circuit 1 shown in FIG.
0 accesses VRAM4 five times. Four of these five accesses are used for still image display and other display processing, and one of the five accesses is for video display. In this case, image data for still image display is prepared in the display section immediately before.

Next, the access operation for video processing will be explained. Now, the electron beam is on the line shown in Figure 8.
Assuming that the display section DS#0 of l ₀ is being scanned,
The image data processing circuit 10 checks whether the moving image pattern specified by the moving image control table No. 0 (see FIG. 4A) exists on the line _l1 one level below. That is, access the 0th byte of the No. 0 video display table and read the Y coordinate data,
The calculation shown in the following equation is performed on this Y coordinate data.

(V(D)+1)-Y(D)=S...(1) However, Y(D): Y coordinate data V(D): Count output of the vertical counter 11 (i.e., operation line number, the top row is 0) If the value S in this formula (1) is “0”, the 9th
As shown in the figure, in the next operation line, the 0th byte of the video pattern is displayed,
Further, when the value S is "7", the seventh byte of the moving image pattern is displayed as shown in the figure. Therefore, if the value S is 0 or more and less than 8,
It can be determined that a video pattern exists.

Next, the image data processing circuit 10 scans the display section DS#1 in the same way as in the case described above, and the moving image pattern specified by the No. 1 moving image control table is displayed on the line one level below. Determine whether it exists or not, and then do the same to display the display section DS#2 to DS
While scanning #31, the existence of the moving image patterns specified by the moving image control tables No. 2 to No. 31 is checked. In this way, the display interval DS of line l ₀
While scanning #0 to DS #31, the image data processing circuit 10 sequentially accesses the 0th byte of the video control tables No. 0 to No. 31, and scans the video pattern on the line one level below. Check for presence. However, in this case, when eight existing moving image patterns are detected, the presence or absence of the existing moving image patterns is not determined thereafter, and even if there are existing moving image patterns, they are ignored. Therefore,
At the time when one line of scanning is completed, the presence of a maximum of eight moving image patterns is detected. Then, the image data processing circuit 10 performs the following processing on the moving image pattern whose existence has been detected during the horizontal non-display period. Now, suppose that the presence of the video patterns specified by the video control tables No. 0 to No. 7 is detected in the lines one level below each (in this case, the video patterns specified by the video control tables No. 8 and later are detected). The image data processing circuit 10 first transfers the X coordinate data of the first byte of the moving image control table No. 0 to the X counter of the moving image processor 20 (the existence of the moving image pattern is ignored). Next, the image data processing circuit 10 accesses the second byte of the moving image control table No. 0, reads the pattern name, and uses the pattern name and the value of S described above to determine the necessary data for the next scan. It calculates what byte of the designated moving image pattern (see FIG. 3) the data is, and transfers 1-byte data corresponding to the calculation result to the pattern shifter 32 of the moving image processor 20. The image data processing circuit 10 also processes the color of the byte corresponding to the value of S described above among the color codes in the memory blocks BC0 to BC31 (see FIG. 5) corresponding to the moving image control table that has undergone the processing described above. The code is read and transferred to the color code register 35 in the video processor.
For example, if the above-mentioned video pattern reading process is performed for the No. 0 video control table and the value of S at this time is 1, then the memory block BC
Transfer the color code in the first byte of 0.

Thereafter, the image data processing circuit 10 and the moving image processing circuit 15 perform the same processing as described above for the moving image control tables No. 1 to No. 7.

Next, the operation of scanning the line _l1 one step below after the horizontal non-display period ends will be described.

For the sake of explanation, let us now focus on the video processor 20 and assume that the data transferred to the X counter 30 in the video processor 20 is "5". First, when the electron beam scanning line _l1 enters the display section DS#0, the X counter 30 lowers the clock signal CK in synchronization with the timing when the dots on the display screen are displayed one by one from the left. Keep counting. As a result, at the fifth count, the count output of the X counter 30 becomes "0", the O detection circuit 31 outputs a "1" signal, the AND gate 33 is opened, and the clock signal CK is supplied to the pattern shifter 32. be done. This results in
The pattern shifter 32 shifts and outputs the ranking data starting from the most significant bit in synchronization with the clock signal CK. Therefore, the pattern signal SPPT is output in synchronization with the display timing of the 6th dot from the left on the display screen (corresponding to 5 on the X coordinate). In this way, the output start timing of the pattern signal SPPT coincides with the X coordinate data transferred to the X counter 30. Note that the pattern signal SPPT is a signal obtained by parallel-to-serial conversion of video pattern data.

When the signal SPPT is output, the buffers 36 to 39 open and close in response to "1" and "0" of this signal, and as a result, only when the signal SPPT becomes "1" does the color code register 35 The color code within is supplied to the color palette 13.

Thereafter, the above-described operations are repeated in sequence. As a result, the video pattern specified by the selected video control table is displayed on the display screen at the position corresponding to the Y and X coordinates in the 0th and 1st bytes of the selected video control table, and It is possible to specify separate colors for each of the 0th to 7th bytes of this moving image pattern. For example, when a video pattern specified by the video control table No.
It is determined by the color code in the 0th to 7th bytes of BCk.

〔Effect of the invention〕

As described above, according to the present invention, there are a plurality of video control tables storing information specifying one of the video patterns and information determining the display position of the specified video pattern, and these video control tables. A plurality of memory blocks are provided corresponding to the video pattern and store color codes specifying colors for each horizontal line of data constituting the video pattern; Since the present invention includes a moving image color control means for controlling the color display of the pattern, the display color of the moving image pattern can be specified for each horizontal line, thereby making it possible to draw moving image patterns with a plurality of color schemes. Therefore, the expressive ability on the display screen can be significantly improved.

[Brief explanation of the drawing]

Figures 1A and 1B are block diagrams showing the configuration of an embodiment of the present invention, and Figure 2 is a VRAM shown in Figure 1A.
3 and 4. A and B are conceptual diagrams showing the stored contents of the moving image pattern table 4d, moving image display table group 4e, and moving image color table 4f shown in FIG. 2, respectively. The figure shows an example of the correspondence between color code, color data, and display color, and FIG. 6 shows the video processing circuit 15.
7 is a block diagram showing the configuration of the video processor, FIG. 8 is a diagram showing the relationship between the display surface and the scanning line in the same embodiment, and FIG. 9 is a video pattern in the same embodiment. FIG. 3 is an explanatory diagram showing the drawing operation of FIG. 4e...Video control table group, BC0 to BC31
. . . storage block, 10 . . . image data processing circuit, 15 . . . moving image processing circuit (10 and 15 are moving image color control means).

Claims (1)

[Claims] 1. In a display controller that controls video display on a display screen based on a plurality of pre-stored video patterns, information specifying one of the video patterns and information determining the display position of the specified video pattern are stored. a plurality of moving image control tables, which are provided corresponding to these moving image control tables, and a plurality of storage blocks in which color codes specifying colors for each horizontal line of data constituting the moving image pattern are stored; A display controller comprising: a video color control means for controlling color display of a video pattern based on the video control table and the contents of the storage block.